freedreno: update generated headers

[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_compute.c

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
index c7635a98c9f6dec9582499701922b532f8607e13..66ed7a4af57f00ac7b440e2daa90d26dc7564f93 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
@@ -70,13 +70,28 @@ fd5_delete_compute_state(struct pipe_context *pctx, void *hwcso)
 
 /* maybe move to fd5_program? */
 static void
-cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
+cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
+               const struct pipe_grid_info *info)
 {
+       const unsigned *local_size = info->block;
        const struct ir3_info *i = &v->info;
        enum a3xx_threadsize thrsz;
+       unsigned instrlen = v->instrlen;
 
-       /* note: blob uses local_size_x/y/z threshold to choose threadsize: */
-       thrsz = FOUR_QUADS;
+       /* if shader is more than 32*16 instructions, don't preload it.  Similar
+        * to the combined restriction of 64*16 for VS+FS
+        */
+       if (instrlen > 32)
+               instrlen = 0;
+
+       /* maybe the limit should be 1024.. basically if we can't have full
+        * occupancy, use TWO_QUAD mode to reduce divergence penalty.
+        */
+       if ((local_size[0] * local_size[1] * local_size[2]) < 512) {
+               thrsz = TWO_QUADS;
+       } else {
+               thrsz = FOUR_QUADS;
+       }
 
        OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
        OUT_RING(ring, 0x00000000);        /* SP_SP_CNTL */
@@ -99,7 +114,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
                A5XX_HLSQ_CS_CONFIG_ENABLED);
 
        OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
-       OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(v->instrlen) |
+       OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(instrlen) |
                COND(v->has_ssbo, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE));
 
        OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
@@ -110,7 +125,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
        unsigned constlen = align(v->constlen, 4) / 4;
        OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
        OUT_RING(ring, constlen);          /* HLSQ_CS_CONSTLEN */
-       OUT_RING(ring, v->instrlen);       /* HLSQ_CS_INSTRLEN */
+       OUT_RING(ring, instrlen);          /* HLSQ_CS_INSTRLEN */
 
        OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
        OUT_RELOC(ring, v->bo, 0, 0, 0);   /* SP_CS_OBJ_START_LO/HI */
@@ -129,7 +144,8 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
                A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
        OUT_RING(ring, 0x1);               /* HLSQ_CS_CNTL_1 */
 
-       fd5_emit_shader(ring, v);
+       if (instrlen > 0)
+               fd5_emit_shader(ring, v);
 }
 
 static void
@@ -144,7 +160,7 @@ emit_setup(struct fd_context *ctx)
        OUT_RING(ring, 0x0);
 
        OUT_PKT7(ring, CP_EVENT_WRITE, 1);
-       OUT_RING(ring, UNK_19);
+       OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
 
        OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
        OUT_RING(ring, 0x00000003);   /* PC_POWER_CNTL */
@@ -165,7 +181,7 @@ static void
 fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
 {
        struct fd5_compute_stateobj *so = ctx->compute;
-       struct ir3_shader_key key = {0};
+       struct ir3_shader_key key = {};
        struct ir3_shader_variant *v;
        struct fd_ringbuffer *ring = ctx->batch->draw;
        unsigned i, nglobal = 0;
@@ -173,9 +189,11 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
        emit_setup(ctx);
 
        v = ir3_shader_variant(so->shader, key, &ctx->debug);
+       if (!v)
+               return;
 
        if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
-               cs_program_emit(ring, v);
+               cs_program_emit(ring, v, info);
 
        fd5_emit_cs_state(ctx, ring, v);
        ir3_emit_cs_consts(v, ring, ctx, info);