freedreno/a5xx: MSAA

[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_gmem.c

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index e16ed1afa111361f3794f7bda6848dc58744bb74..4a883eefd5cbe38f6368144cee5ddda1d1418cdd 100644 (file)
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -49,12 +49,6 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
        enum a5xx_tile_mode tile_mode;
        unsigned i;
 
-       if (gmem) {
-               tile_mode = TILE5_2;
-       } else {
-               tile_mode = TILE5_LINEAR;
-       }
-
        for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
                enum a5xx_color_fmt format = 0;
                enum a3xx_color_swap swap = WZYX;
@@ -66,6 +60,12 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
                uint32_t base = 0;
                uint32_t offset = 0;
 
+               if (gmem) {
+                       tile_mode = TILE5_2;
+               } else {
+                       tile_mode = TILE5_LINEAR;
+               }
+
                if ((i < nr_bufs) && bufs[i]) {
                        struct pipe_surface *psurf = bufs[i];
                        enum pipe_format pformat = psurf->format;
@@ -85,12 +85,15 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
                                        psurf->u.tex.first_layer);
 
                        if (gmem) {
-                               stride = gmem->bin_w * rsc->cpp;
+                               stride = gmem->bin_w * gmem->cbuf_cpp[i];
                                size = stride * gmem->bin_h;
                                base = gmem->cbuf_base[i];
                        } else {
                                stride = slice->pitch * rsc->cpp;
                                size = slice->size0;
+
+                               if (!fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
+                                       tile_mode = rsc->tile_mode;
                        }
                }
 
@@ -488,7 +491,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
 
                OUT_PKT4(ring, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
                OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
-                               A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR) |
+                               A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
                                A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX));
                OUT_RING(ring, A5XX_RB_MRT_PITCH(slice->pitch * rsc->cpp));
                OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(slice->size0));
@@ -577,21 +580,23 @@ fd5_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
        emit_zs(ring, pfb->zsbuf, gmem);
        emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem);
 
-       // TODO MSAA
+       enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
+
        OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
-       OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
-       OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
-                       A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
+       OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(samples));
+       OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
+                       COND(samples == MSAA_ONE, A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
 
        OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
-       OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
-       OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
-                       A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
+       OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
+       OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
+                       COND(samples == MSAA_ONE, A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
+
 
        OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
-       OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
-       OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
-                       A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
+       OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(samples));
+       OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(samples) |
+                       COND(samples == MSAA_ONE, A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE));
 }
 
 
@@ -606,6 +611,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
        struct fd_ringbuffer *ring = batch->gmem;
        struct fd_resource *rsc = fd_resource(psurf->texture);
        struct fd_resource_slice *slice;
+       bool tiled;
        uint32_t offset;
 
        if (buf == BLIT_S)
@@ -623,8 +629,12 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
        OUT_RING(ring, 0x00000000);   /* RB_BLIT_FLAG_DST_PITCH */
        OUT_RING(ring, 0x00000000);   /* RB_BLIT_FLAG_DST_ARRAY_PITCH */
 
+       tiled = rsc->tile_mode &&
+               !fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
+
        OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_3, 5);
-       OUT_RING(ring, 0x00000004);   /* XXX RB_RESOLVE_CNTL_3 */
+       OUT_RING(ring, 0x00000004 |   /* XXX RB_RESOLVE_CNTL_3 */
+                       COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED));
        OUT_RELOCW(ring, rsc->bo, offset, 0, 0);     /* RB_BLIT_DST_LO/HI */
        OUT_RING(ring, A5XX_RB_BLIT_DST_PITCH(slice->pitch * rsc->cpp));
        OUT_RING(ring, A5XX_RB_BLIT_DST_ARRAY_PITCH(slice->size0));
@@ -632,6 +642,12 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
        OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
        OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(buf));
 
+       struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+//     bool msaa_resolve = pfb->samples > 1;
+       bool msaa_resolve = false;
+       OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
+       OUT_RING(ring, COND(msaa_resolve, A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE));
+
        fd5_emit_blit(batch->ctx, ring);
 }
 
@@ -692,7 +708,7 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
        OUT_RING(ring, 0x0);
 
        OUT_PKT7(ring, CP_EVENT_WRITE, 1);
-       OUT_RING(ring, UNK_19);
+       OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
 
        OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
        OUT_RING(ring, 0x00000003);   /* PC_POWER_CNTL */
@@ -734,7 +750,6 @@ fd5_emit_sysmem_prep(struct fd_batch *batch)
        emit_zs(ring, pfb->zsbuf, NULL);
        emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
 
-       // TODO MSAA
        OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
        OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
        OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |