freedreno: add adreno 650

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_context.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.c b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
index ec8b871a28fdf230b12050b2fcccb3f4f374d97c..6ccc45ab658e050b1a6e1c98864a185933bbe181 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_context.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
@@ -50,10 +50,10 @@ fd6_context_destroy(struct pipe_context *pctx)
 
        fd_context_destroy(pctx);
 
-       if (fd6_ctx->vsc_data)
-               fd_bo_del(fd6_ctx->vsc_data);
-       if (fd6_ctx->vsc_data2)
-               fd_bo_del(fd6_ctx->vsc_data2);
+       if (fd6_ctx->vsc_draw_strm)
+               fd_bo_del(fd6_ctx->vsc_draw_strm);
+       if (fd6_ctx->vsc_prim_strm)
+               fd_bo_del(fd6_ctx->vsc_prim_strm);
        fd_bo_del(fd6_ctx->control_mem);
 
        fd_context_cleanup_common_vbos(&fd6_ctx->base);
@@ -77,6 +77,7 @@ static const uint8_t primtypes[] = {
                [PIPE_PRIM_LINE_STRIP_ADJACENCY]        = DI_PT_LINESTRIP_ADJ,
                [PIPE_PRIM_TRIANGLES_ADJACENCY]         = DI_PT_TRI_ADJ,
                [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]    = DI_PT_TRISTRIP_ADJ,
+               [PIPE_PRIM_PATCHES]                     = DI_PT_PATCHES0,
                [PIPE_PRIM_MAX]                         = DI_PT_RECTLIST,  /* internal clear blits */
 };
 
@@ -92,14 +93,57 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
 
 
        switch (screen->gpu_id) {
+       case 618:
+/*
+GRAS_BIN_CONTROL:
+RB_BIN_CONTROL:
+  - a618 doesn't appear to set .USE_VIZ; also bin size diffs
+
+RB_CCU_CNTL:
+  - 0x3c400004 -> 0x3e400004
+  - 0x10000000 -> 0x08000000
+
+RB_UNKNOWN_8E04:               <-- see stencil-0000.rd.gz
+  - 0x01000000 -> 0x00100000
+
+SP_UNKNOWN_A0F8:
+PC_UNKNOWN_9805:
+  - 0x1 -> 0
+ */
+               fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
+               fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x7c000) |
+                                                                                 A6XX_RB_CCU_CNTL_GMEM |
+                                                                                 A6XX_RB_CCU_CNTL_UNK2;
+               fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x10000);
+               fd6_ctx->magic.PC_UNKNOWN_9805 = 0x0;
+               fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x0;
+               break;
        case 630:
                fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
-               // NOTE: newer blob using 0x3c400004, need to revisit:
-               fd6_ctx->magic.RB_CCU_CNTL_gmem     = 0x7c400004;
-               fd6_ctx->magic.RB_CCU_CNTL_bypass   = 0x10000000;
+               fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
+                                                                                 A6XX_RB_CCU_CNTL_GMEM |
+                                                                                 A6XX_RB_CCU_CNTL_UNK2;
+               fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
                fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
                fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
                break;
+       case 640:
+               fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
+               fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
+                                                                                 A6XX_RB_CCU_CNTL_GMEM;
+               fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
+               fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
+               fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
+       case 650:
+               fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x04100000;
+               fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x114000) |
+                                                                                 A6XX_RB_CCU_CNTL_GMEM;
+               fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x30000);
+               fd6_ctx->magic.PC_UNKNOWN_9805 = 0x2;
+               fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x2;
+               break;
+       default:
+               unreachable("missing magic config");
        }
 
        pctx = &fd6_ctx->base.base;
@@ -119,6 +163,7 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
        fd6_texture_init(pctx);
        fd6_prog_init(pctx);
        fd6_emit_init(pctx);
+       fd6_query_context_init(pctx);
 
        pctx = fd_context_init(&fd6_ctx->base, pscreen, primtypes, priv, flags);
        if (!pctx)
@@ -132,20 +177,20 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
        /* fd_context_init overwrites delete_rasterizer_state, so set this
         * here. */
        pctx->delete_rasterizer_state = fd6_rasterizer_state_delete;
+       pctx->delete_blend_state = fd6_blend_state_delete;
        pctx->delete_depth_stencil_alpha_state = fd6_depth_stencil_alpha_state_delete;
 
        /* initial sizes for VSC buffers (or rather the per-pipe sizes
         * which is used to derive entire buffer size:
         */
-       fd6_ctx->vsc_data_pitch = 0x440;
-       fd6_ctx->vsc_data2_pitch = 0x1040;
+       fd6_ctx->vsc_draw_strm_pitch = 0x440;
+       fd6_ctx->vsc_prim_strm_pitch = 0x1040;
 
        fd6_ctx->control_mem = fd_bo_new(screen->dev, 0x1000,
                        DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
 
        fd_context_setup_common_vbos(&fd6_ctx->base);
 
-       fd6_query_context_init(pctx);
        fd6_blitter_init(pctx);
 
        fd6_ctx->border_color_uploader = u_upload_create(pctx, 4096, 0,