freedreno/a6xx: cleanup magic registers

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_context.h

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.h b/src/gallium/drivers/freedreno/a6xx/fd6_context.h
index f3cdd44dec433f0b7b29a706cee463025c4f11e7..0d810d350e9569099b44fa97512e1fbe5ccd6750 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_context.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.h
@@ -32,15 +32,13 @@
 
 #include "freedreno_context.h"
 
-#include "ir3_shader.h"
+#include "ir3/ir3_shader.h"
 
 #include "a6xx.xml.h"
 
 struct fd6_context {
        struct fd_context base;
 
-       struct fd_bo *vs_pvt_mem, *fs_pvt_mem;
-
        /* Two buffers related to hw binning / visibility stream (VSC).
         * Compared to previous generations
         *   (1) we cannot specify individual buffers per VSC, instead
@@ -50,18 +48,12 @@ struct fd6_context {
         */
        struct fd_bo *vsc_data, *vsc_data2;
 
-// TODO annoyingly large sizes to prevent hangs with larger amounts
-// of geometry, like aquarium with max # of fish.  Need to figure
-// out how to calculate the required size.
-#define A6XX_VSC_DATA_PITCH  0x4400
-#define A6XX_VSC_DATA2_PITCH 0x10400
+       unsigned vsc_data_pitch, vsc_data2_pitch;
 
-       /* TODO not sure what this is for.. probably similar to
-        * CACHE_FLUSH_TS on kernel side, where value gets written
-        * to this address synchronized w/ 3d (ie. a way to
-        * synchronize when the CP is running far ahead)
+       /* The 'control' mem BO is used for various housekeeping
+        * functions.  See 'struct fd6_control'
         */
-       struct fd_bo *blit_mem;
+       struct fd_bo *control_mem;
        uint32_t seqno;
 
        struct u_upload_mgr *border_color_uploader;
@@ -80,9 +72,6 @@ struct fd6_context {
         */
        uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 
-       /* bitmask of samplers which need astc srgb workaround: */
-       uint16_t vastc_srgb, fastc_srgb;
-
        /* some state changes require a different shader variant.  Keep
         * track of this so we know when we need to re-emit shader state
         * due to variant change.  See fixup_shader_state()
@@ -102,6 +91,18 @@ struct fd6_context {
 
        uint16_t tex_seqno;
        struct hash_table *tex_cache;
+
+       /* collection of magic register values which differ between
+        * various different a6xx
+        */
+       struct {
+               uint32_t RB_UNKNOWN_8E04_blit;    /* value for CP_BLIT's */
+               uint32_t RB_CCU_CNTL_bypass;      /* for sysmem rendering */
+               uint32_t RB_CCU_CNTL_gmem;        /* for GMEM rendering */
+               uint32_t PC_UNKNOWN_9805;
+               uint32_t SP_UNKNOWN_A0F8;
+
+       } magic;
 };
 
 static inline struct fd6_context *
@@ -113,6 +114,30 @@ fd6_context(struct fd_context *ctx)
 struct pipe_context *
 fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags);
 
+
+/* This struct defines the layout of the fd6_context::control buffer: */
+struct fd6_control {
+       uint32_t seqno;          /* seqno for async CP_EVENT_WRITE, etc */
+       uint32_t _pad0;
+       volatile uint32_t vsc_overflow;
+       uint32_t _pad1;
+       /* flag set from cmdstream when VSC overflow detected: */
+       uint32_t vsc_scratch;
+       uint32_t _pad2;
+       uint32_t _pad3;
+       uint32_t _pad4;
+
+       /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */
+       struct {
+               uint32_t offset;
+               uint32_t pad[7];
+       } flush_base[4];
+};
+
+#define control_ptr(fd6_ctx, member)  \
+       (fd6_ctx)->control_mem, offsetof(struct fd6_control, member), 0, 0
+
+
 static inline void
 emit_marker6(struct fd_ringbuffer *ring, int scratch_idx)
 {