freedreno/batch: replace lrz_clear with prologue

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_draw.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index ab8fdea19de7b6afb6559565eab0971a1559cd10..3e9ec98d5fca5d486e79c26a68b812be7c68f464 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -178,10 +178,16 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
                .primitive_restart = info->primitive_restart && info->index_size,
        };
 
+       if (!(ctx->prog.vs && ctx->prog.fs))
+               return false;
+
        if (info->mode == PIPE_PRIM_PATCHES) {
                emit.key.hs = ctx->prog.hs;
                emit.key.ds = ctx->prog.ds;
 
+               if (!(ctx->prog.hs && ctx->prog.ds))
+                       return false;
+
                shader_info *ds_info = &emit.key.ds->nir->info;
                emit.key.key.tessellation = ir3_tess_mode(ds_info->tess.primitive_mode);
        }
@@ -204,6 +210,8 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
        if (!fd6_ctx->prog)
                return NULL;
 
+       fixup_draw_state(ctx, &emit);
+
        emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
        emit.bs = fd6_emit_get_prog(&emit)->bs;
        emit.vs = fd6_emit_get_prog(&emit)->vs;
@@ -297,8 +305,6 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
                ctx->last.restart_index = restart_index;
        }
 
-       fixup_draw_state(ctx, &emit);
-
        fd6_emit_state(ring, &emit);
 
        /* for debug after a lock up, write a unique counter value
@@ -339,12 +345,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
        struct fd_ringbuffer *ring;
        struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 
-       if (batch->lrz_clear) {
-               fd_ringbuffer_del(batch->lrz_clear);
-       }
-
-       batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
-       ring = batch->lrz_clear;
+       ring = fd_batch_get_prologue(batch);
 
        emit_marker6(ring, 7);
        OUT_PKT7(ring, CP_SET_MARKER, 1);
@@ -375,7 +376,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
        OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE));
        emit_marker6(ring, 7);
 
-       OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
+       OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
        OUT_RING(ring, 0x0);
 
        OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
@@ -418,18 +419,18 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
                        A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
                        A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
        OUT_RELOC(ring, zsbuf->lrz, 0, 0, 0);
-       OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
+       OUT_RING(ring, A6XX_RB_2D_DST_PITCH(zsbuf->lrz_pitch * 2).value);
        OUT_RING(ring, 0x00000000);
        OUT_RING(ring, 0x00000000);
        OUT_RING(ring, 0x00000000);
        OUT_RING(ring, 0x00000000);
        OUT_RING(ring, 0x00000000);
 
-       OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
-       OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
-       OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
-       OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
-       OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
+       OUT_REG(ring,
+                       A6XX_GRAS_2D_SRC_TL_X(0),
+                       A6XX_GRAS_2D_SRC_BR_X(0),
+                       A6XX_GRAS_2D_SRC_TL_Y(0),
+                       A6XX_GRAS_2D_SRC_BR_Y(0));
 
        OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
        OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |