static void
draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum pc_di_primtype primtype,
- enum pc_di_vis_cull_mode vismode,
const struct pipe_draw_info *info,
unsigned index_offset)
{
static void
draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum pc_di_primtype primtype,
- enum pc_di_vis_cull_mode vismode,
const struct pipe_draw_info *info,
unsigned index_offset)
{
0x2000;
OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
- if (vismode == USE_VISIBILITY) {
- OUT_RINGP(ring, draw, &batch->draw_patches);
- } else {
- OUT_RING(ring, draw);
- }
+ OUT_RINGP(ring, draw, &batch->draw_patches);
OUT_RING(ring, info->instance_count); /* NumInstances */
OUT_RING(ring, info->count); /* NumIndices */
OUT_RING(ring, 0x0); /* XXX */
0x2000;
OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
- if (vismode == USE_VISIBILITY) {
- OUT_RINGP(ring, draw, &batch->draw_patches);
- } else {
- OUT_RING(ring, draw);
- }
+ OUT_RINGP(ring, draw, &batch->draw_patches);
OUT_RING(ring, info->instance_count); /* NumInstances */
OUT_RING(ring, info->count); /* NumIndices */
}
}
-static void
-draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
- struct fd6_emit *emit, unsigned index_offset)
-{
- const struct pipe_draw_info *info = emit->info;
- enum pc_di_primtype primtype = ctx->primtypes[info->mode];
-
- fd6_emit_state(ctx, ring, emit);
-
- if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
- fd6_emit_vertex_bufs(ring, emit);
-
- OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
- OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
- OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
-
- OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
- OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
- info->restart_index : 0xffffffff);
-
- /* for debug after a lock up, write a unique counter value
- * to scratch7 for each draw, to make it easier to match up
- * register dumps to cmdstream. The combination of IB
- * (scratch6) and DRAW is enough to "triangulate" the
- * particular draw that caused lockup.
- */
- emit_marker6(ring, 7);
-
- if (info->indirect) {
- draw_emit_indirect(ctx->batch, ring, primtype,
- emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
- info, index_offset);
- } else {
- draw_emit(ctx->batch, ring, primtype,
- emit->binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
- info, index_offset);
- }
-
- emit_marker6(ring, 7);
- fd_reset_wfi(ctx->batch);
-}
-
/* fixup dirty shader state in case some "unrelated" (from the state-
* tracker's perspective) state change causes us to switch to a
* different variant.
fixup_shader_state(ctx, &emit.key.key);
- unsigned dirty = ctx->dirty;
-
- if (!(dirty & FD_DIRTY_PROG)) {
+ if (!(ctx->dirty & FD_DIRTY_PROG)) {
emit.prog = fd6_ctx->prog;
} else {
fd6_ctx->prog = fd6_emit_get_prog(&emit);
}
+ emit.dirty = ctx->dirty; /* *after* fixup_shader_state() */
+ emit.bs = fd6_emit_get_prog(&emit)->bs;
emit.vs = fd6_emit_get_prog(&emit)->vs;
emit.fs = fd6_emit_get_prog(&emit)->fs;
*/
emit.no_lrz_write = fp->writes_pos || fp->has_kill;
- emit.binning_pass = false;
- emit.dirty = dirty;
+ struct fd_ringbuffer *ring = ctx->batch->draw;
+ enum pc_di_primtype primtype = ctx->primtypes[info->mode];
- draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
+ fd6_emit_state(ring, &emit);
+
+ OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
+ OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
+ OUT_RING(ring, info->start_instance); /* VFD_INSTANCE_START_OFFSET */
+
+ OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
+ OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
+ info->restart_index : 0xffffffff);
+
+ /* for debug after a lock up, write a unique counter value
+ * to scratch7 for each draw, to make it easier to match up
+ * register dumps to cmdstream. The combination of IB
+ * (scratch6) and DRAW is enough to "triangulate" the
+ * particular draw that caused lockup.
+ */
+ emit_marker6(ring, 7);
- /* and now binning pass: */
- emit.binning_pass = true;
- emit.dirty = dirty & ~(FD_DIRTY_BLEND);
- emit.vs = fd6_emit_get_prog(&emit)->bs;
+ if (info->indirect) {
+ draw_emit_indirect(ctx->batch, ring, primtype,
+ info, index_offset);
+ } else {
+ draw_emit(ctx->batch, ring, primtype,
+ info, index_offset);
+ }
- draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
+ emit_marker6(ring, 7);
+ fd_reset_wfi(ctx->batch);
if (emit.streamout_mask) {
struct fd_ringbuffer *ring = ctx->batch->draw;
return true;
}
-static bool is_z32(enum pipe_format format)
-{
- switch (format) {
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- case PIPE_FORMAT_Z32_UNORM:
- case PIPE_FORMAT_Z32_FLOAT:
- return true;
- default:
- return false;
- }
-}
-
static void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
{
// draw
if (!batch->lrz_clear) {
- batch->lrz_clear = fd_ringbuffer_new(batch->ctx->pipe, 0x1000);
- fd_ringbuffer_set_parent(batch->lrz_clear, batch->gmem);
+ batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
}
ring = batch->lrz_clear;
fd6_cache_flush(batch, ring);
}
+static bool is_z32(enum pipe_format format)
+{
+ switch (format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ case PIPE_FORMAT_Z32_UNORM:
+ case PIPE_FORMAT_Z32_FLOAT:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool
fd6_clear(struct fd_context *ctx, unsigned buffers,
const union pipe_color_union *color, double depth, unsigned stencil)
{
struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
- struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
- struct fd_ringbuffer *ring = ctx->batch->draw;
-
- if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
- is_z32(pfb->zsbuf->format))
+ const bool has_depth = pfb->zsbuf;
+ unsigned color_buffers = buffers >> 2;
+ unsigned i;
+
+ /* If we're clearing after draws, fallback to 3D pipe clears. We could
+ * use blitter clears in the draw batch but then we'd have to patch up the
+ * gmem offsets. This doesn't seem like a useful thing to optimize for
+ * however.*/
+ if (ctx->batch->num_draws > 0)
return false;
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
- OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(scissor->minx) |
- A6XX_RB_BLIT_SCISSOR_TL_Y(scissor->miny));
- OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(scissor->maxx - 1) |
- A6XX_RB_BLIT_SCISSOR_BR_Y(scissor->maxy - 1));
-
- if (buffers & PIPE_CLEAR_COLOR) {
- for (int i = 0; i < pfb->nr_cbufs; i++) {
- union util_color uc = {0};
-
- if (!pfb->cbufs[i])
- continue;
-
- if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
- continue;
-
- enum pipe_format pfmt = pfb->cbufs[i]->format;
-
- // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
- union pipe_color_union swapped;
- switch (fd6_pipe2swap(pfmt)) {
- case WZYX:
- swapped.ui[0] = color->ui[0];
- swapped.ui[1] = color->ui[1];
- swapped.ui[2] = color->ui[2];
- swapped.ui[3] = color->ui[3];
- break;
- case WXYZ:
- swapped.ui[2] = color->ui[0];
- swapped.ui[1] = color->ui[1];
- swapped.ui[0] = color->ui[2];
- swapped.ui[3] = color->ui[3];
- break;
- case ZYXW:
- swapped.ui[3] = color->ui[0];
- swapped.ui[0] = color->ui[1];
- swapped.ui[1] = color->ui[2];
- swapped.ui[2] = color->ui[3];
- break;
- case XYZW:
- swapped.ui[3] = color->ui[0];
- swapped.ui[2] = color->ui[1];
- swapped.ui[1] = color->ui[2];
- swapped.ui[0] = color->ui[3];
- break;
- }
-
- if (util_format_is_pure_uint(pfmt)) {
- util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
- } else if (util_format_is_pure_sint(pfmt)) {
- util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
- } else {
- util_pack_color(swapped.f, pfmt, &uc);
- }
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
- OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
- OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
- A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
- OUT_RINGP(ring, i, &ctx->batch->gmem_patches);
-
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
- OUT_RING(ring, 0);
+ foreach_bit(i, color_buffers)
+ ctx->batch->clear_color[i] = *color;
+ if (buffers & PIPE_CLEAR_DEPTH)
+ ctx->batch->clear_depth = depth;
+ if (buffers & PIPE_CLEAR_STENCIL)
+ ctx->batch->clear_stencil = stencil;
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
- OUT_RING(ring, uc.ui[0]);
- OUT_RING(ring, uc.ui[1]);
- OUT_RING(ring, uc.ui[2]);
- OUT_RING(ring, uc.ui[3]);
+ ctx->batch->fast_cleared |= buffers;
- fd6_emit_blit(ctx->batch, ring);
- }
- }
-
- if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
- enum pipe_format pfmt = pfb->zsbuf->format;
- uint32_t clear = util_pack_z_stencil(pfmt, depth, stencil);
- uint32_t mask = 0;
-
- if (buffers & PIPE_CLEAR_DEPTH)
- mask |= 0x1;
-
- if (buffers & PIPE_CLEAR_STENCIL)
- mask |= 0x2;
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
- OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
- OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
- // XXX UNK0 for separate stencil ??
- A6XX_RB_BLIT_INFO_DEPTH |
- A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
- OUT_RINGP(ring, MAX_RENDER_TARGETS, &ctx->batch->gmem_patches);
-
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
- OUT_RING(ring, 0);
-
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
- OUT_RING(ring, clear);
-
- fd6_emit_blit(ctx->batch, ring);
-
- if (pfb->zsbuf && (buffers & PIPE_CLEAR_DEPTH)) {
- struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
- if (zsbuf->lrz) {
- zsbuf->lrz_valid = true;
- fd6_clear_lrz(ctx->batch, zsbuf, depth);
- }
+ if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
+ struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
+ if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
+ zsbuf->lrz_valid = true;
+ fd6_clear_lrz(ctx->batch, zsbuf, depth);
}
}
projects / mesa.git / blobdiff