#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_helpers.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/u_viewport.h"
#include "freedreno_resource.h"
OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D) |
A6XX_TEX_CONST_2_FETCHSIZE(TFETCH6_2_BYTE),
&ctx->batch->fb_read_patches);
- OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size));
+ OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
enum fd6_state_id state_id;
unsigned enable_mask;
} s[PIPE_SHADER_TYPES] = {
- [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, 0x7 },
- [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, 0x7 },
- [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, 0x7 },
- [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, 0x7 },
- [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, 0x6 },
+ [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
+ [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
+ [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
+ [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
+ [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
};
debug_assert(s[type].state_id);
static struct fd_ringbuffer *
build_lrz(struct fd6_emit *emit, bool binning_pass)
{
+ struct fd6_blend_stateobj *blend = fd6_blend_stateobj(emit->ctx->blend);
struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(emit->ctx->zsa);
struct pipe_framebuffer_state *pfb = &emit->ctx->batch->framebuffer;
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
16, FD_RINGBUFFER_STREAMING);
- if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
+ if (zsa->invalidate_lrz) {
+ rsc->lrz_valid = false;
gras_lrz_cntl = 0;
rb_lrz_cntl = 0;
- } else if (binning_pass && zsa->lrz_write) {
+ } else if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
+ gras_lrz_cntl = 0;
+ rb_lrz_cntl = 0;
+ } else if (binning_pass && blend->lrz_write && zsa->lrz_write) {
gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
}
} else {
OUT_PKT7(ring, CP_MEM_TO_REG, 3);
OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
- CP_MEM_TO_REG_0_64B | CP_MEM_TO_REG_0_ACCUMULATE |
- CP_MEM_TO_REG_0_CNT(1 - 1));
+ CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
+ CP_MEM_TO_REG_0_CNT(0));
OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
}
emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
}
- fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, 0x7);
+ fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
}
static void
struct fd_ringbuffer *state;
state = build_vbo_state(emit, emit->vs);
- fd6_emit_take_group(emit, state, FD6_GROUP_VBO, 0x7);
+ fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
}
if (dirty & FD_DIRTY_ZSA) {
struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
- fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, 0x7);
+ fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
else
- fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, 0x7);
+ fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
}
- if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && pfb->zsbuf) {
+ if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) && pfb->zsbuf) {
struct fd_ringbuffer *state;
state = build_lrz(emit, false);
- fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, 0x6);
+ fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
state = build_lrz(emit, true);
- fd6_emit_take_group(emit, state, FD6_GROUP_LRZ_BINNING, 0x1);
+ fd6_emit_take_group(emit, state,
+ FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
}
if (dirty & FD_DIRTY_STENCIL_REF) {
}
if (dirty & FD_DIRTY_PROG) {
- fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, 0x7);
- fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, 0x6);
+ fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
+ fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
fd6_emit_add_group(emit, prog->binning_stateobj,
- FD6_GROUP_PROG_BINNING, 0x1);
+ FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
- /* emit remaining non-stateobj program state, ie. what depends
- * on other emit state, so cannot be pre-baked. This could
- * be moved to a separate stateobj which is dynamically
- * created.
+ /* emit remaining streaming program state, ie. what depends on
+ * other emit state, so cannot be pre-baked.
*/
- fd6_program_emit(ring, emit);
- }
+ struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
- if (dirty & FD_DIRTY_RASTERIZER) {
- struct fd6_rasterizer_stateobj *rasterizer =
- fd6_rasterizer_stateobj(ctx->rasterizer);
- fd6_emit_add_group(emit, rasterizer->stateobj,
- FD6_GROUP_RASTERIZER, 0x7);
+ fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
}
- /* Since the primitive restart state is not part of a tracked object, we
- * re-emit this register every time.
- */
- if (emit->info && ctx->rasterizer) {
- struct fd6_rasterizer_stateobj *rasterizer =
- fd6_rasterizer_stateobj(ctx->rasterizer);
- OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9806, 1);
- OUT_RING(ring, 0);
- OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9990, 1);
- OUT_RING(ring, 0);
- OUT_PKT4(ring, REG_A6XX_VFD_UNKNOWN_A008, 1);
- OUT_RING(ring, 0);
-
- OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_0, 1);
- OUT_RING(ring, rasterizer->pc_primitive_cntl |
- COND(emit->info->primitive_restart && emit->info->index_size,
- A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART));
+ if (dirty & FD_DIRTY_RASTERIZER) {
+ struct fd_ringbuffer *stateobj =
+ fd6_rasterizer_state(ctx, emit->primitive_restart);
+ fd6_emit_add_group(emit, stateobj,
+ FD6_GROUP_RASTERIZER, ENABLE_ALL);
}
if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
+ struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
+ emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
+
unsigned nr = pfb->nr_cbufs;
if (ctx->rasterizer->rasterizer_discard)
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
+
+ fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
}
- fd6_emit_consts(emit, vs, PIPE_SHADER_VERTEX, FD6_GROUP_VS_CONST, 0x7);
- fd6_emit_consts(emit, hs, PIPE_SHADER_TESS_CTRL, FD6_GROUP_HS_CONST, 0x7);
- fd6_emit_consts(emit, ds, PIPE_SHADER_TESS_EVAL, FD6_GROUP_DS_CONST, 0x7);
- fd6_emit_consts(emit, gs, PIPE_SHADER_GEOMETRY, FD6_GROUP_GS_CONST, 0x7);
- fd6_emit_consts(emit, fs, PIPE_SHADER_FRAGMENT, FD6_GROUP_FS_CONST, 0x6);
+ fd6_emit_consts(emit, vs, PIPE_SHADER_VERTEX, FD6_GROUP_VS_CONST, ENABLE_ALL);
+ fd6_emit_consts(emit, hs, PIPE_SHADER_TESS_CTRL, FD6_GROUP_HS_CONST, ENABLE_ALL);
+ fd6_emit_consts(emit, ds, PIPE_SHADER_TESS_EVAL, FD6_GROUP_DS_CONST, ENABLE_ALL);
+ fd6_emit_consts(emit, gs, PIPE_SHADER_GEOMETRY, FD6_GROUP_GS_CONST, ENABLE_ALL);
+ fd6_emit_consts(emit, fs, PIPE_SHADER_FRAGMENT, FD6_GROUP_FS_CONST, ENABLE_DRAW);
if (emit->key.key.has_gs || emit->key.key.tessellation)
fd6_emit_tess_const(emit);
struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
- fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, 0x7);
+ fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
} else {
- fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, 0x7);
+ fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
}
struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
uint32_t i;
for (i = 0; i < pfb->nr_cbufs; i++) {
- enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
- bool is_int = util_format_is_pure_integer(format);
- bool has_alpha = util_format_has_alpha(format);
- uint32_t control = blend->rb_mrt[i].control;
- uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
-
- if (is_int) {
- control &= A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
- control |= A6XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
- }
-
- if (has_alpha) {
- blend_control |= blend->rb_mrt[i].blend_control_rgb;
- } else {
- blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
- control &= ~A6XX_RB_MRT_CONTROL_BLEND2;
- }
-
OUT_PKT4(ring, REG_A6XX_RB_MRT_CONTROL(i), 1);
- OUT_RING(ring, control);
+ OUT_RING(ring, blend->rb_mrt[i].control);
OUT_PKT4(ring, REG_A6XX_RB_MRT_BLEND_CONTROL(i), 1);
- OUT_RING(ring, blend_control);
+ OUT_RING(ring, blend->rb_mrt[i].blend_control);
}
OUT_PKT4(ring, REG_A6XX_RB_DITHER_CNTL, 1);
emit_border_color(ctx, ring);
if (hs) {
- debug_assert(hs->image_mapping.num_ibo == 0);
- debug_assert(ds->image_mapping.num_ibo == 0);
+ debug_assert(ir3_shader_nibo(hs) == 0);
+ debug_assert(ir3_shader_nibo(ds) == 0);
}
if (gs) {
- debug_assert(gs->image_mapping.num_ibo == 0);
+ debug_assert(ir3_shader_nibo(gs) == 0);
}
#define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
- const struct ir3_ibo_mapping *mapping = &fs->image_mapping;
OUT_PKT7(obj, CP_LOAD_STATE6, 3);
OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
- CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
+ CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
OUT_RB(obj, state);
OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
* de-duplicate this from program->config_stateobj
*/
OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
- OUT_RING(obj, mapping->num_ibo);
+ OUT_RING(obj, ir3_shader_nibo(fs));
ir3_emit_ssbo_sizes(ctx->screen, fs, obj,
&ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
ir3_emit_image_dims(ctx->screen, fs, obj,
&ctx->shaderimg[PIPE_SHADER_FRAGMENT]);
- fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, 0x6);
+ fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
fd_ringbuffer_del(state);
}
unsigned n = g->stateobj ?
fd_ringbuffer_size(g->stateobj) / 4 : 0;
+ debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
+
if (n == 0) {
OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
CP_SET_DRAW_STATE__0_DISABLE |
- CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
+ g->enable_mask |
CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
} else {
OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
- CP_SET_DRAW_STATE__0_ENABLE_MASK(g->enable_mask) |
+ g->enable_mask |
CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
OUT_RB(ring, g->stateobj);
}
if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
struct fd_ringbuffer *state =
fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
- const struct ir3_ibo_mapping *mapping = &cp->image_mapping;
OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
- CP_LOAD_STATE6_0_NUM_UNIT(mapping->num_ibo));
+ CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
- OUT_RING(ring, mapping->num_ibo);
+ OUT_RING(ring, ir3_shader_nibo(cp));
fd_ringbuffer_del(state);
}
WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
- WRITE(REG_A6XX_VFD_UNKNOWN_A009, 0x00000001);
+ WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
+ WRITE(REG_A6XX_PC_UNKNOWN_9990, 0);
WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
seqno = fd6_event_write(batch, ring, CACHE_FLUSH_AND_INV_EVENT, true);
OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
- OUT_RING(ring, 0x00000013);
+ OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
+ CP_WAIT_REG_MEM_0_POLL_MEMORY);
OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
- OUT_RING(ring, seqno);
- OUT_RING(ring, 0xffffffff);
- OUT_RING(ring, 0x00000010);
+ OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
+ OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
+ OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, UNK_1C, true);
fd6_event_write(batch, ring, 0x31, false);
- OUT_PKT7(ring, CP_UNK_A6XX_14, 4);
- OUT_RING(ring, 0x00000000);
+ OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
+ OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
- OUT_RING(ring, seqno);
+ OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
}
void
projects / mesa.git / blobdiff