freedreno/a6xx: Remove unnecessary GRAS_2D_BLIT_INFO write

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index c3823d85437785ce33922842790558bb9bcfbf7f..45bb5250ec8e050aaf83809421b8820091895ab6 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -608,13 +608,13 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
                OUT_RING(ring,
                                 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[0]) |
-                                A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[0]));
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
+                                A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
        }
 
        if (dirty & FD_DIRTY_ZSA) {
@@ -632,20 +632,25 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
        }
 
        if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
-               struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
                struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
 
                if (pfb->zsbuf) {
                        struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
                        uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
+                       uint32_t rb_lrz_cntl = zsa->rb_lrz_cntl;
 
-                       if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
+                       if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid) {
                                gras_lrz_cntl = 0;
-                       else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
+                               rb_lrz_cntl = 0;
+                       } else if (emit->key.binning_pass && zsa->lrz_write) {
                                gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_LRZ_WRITE;
+                       }
 
                        OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
                        OUT_RING(ring, gras_lrz_cntl);
+
+                       OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
+                       OUT_RING(ring, rb_lrz_cntl);
                }
        }
 
@@ -654,7 +659,8 @@ fd6_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
                struct pipe_stencil_ref *sr = &ctx->stencil_ref;
 
                OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 3);
-               OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]));  // TODO bf?
+               OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
+                               A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
                OUT_RING(ring, zsa->rb_stencilmask);
                OUT_RING(ring, zsa->rb_stencilwrmask);
        }
@@ -1034,8 +1040,6 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
        OUT_RING(ring, 0);
 
        WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
-       WRITE(REG_A6XX_GRAS_2D_BLIT_INFO,
-                 A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(RB6_R8G8B8_UNORM));
        WRITE(REG_A6XX_GRAS_UNKNOWN_8109, 0);
        WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0);
 
@@ -1157,6 +1161,12 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 
        OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
        OUT_RING(ring, 0x00000000);
+
+       OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
+       OUT_RING(ring, 0x00000000);
+
+       OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
+       OUT_RING(ring, 0x00000000);
 }
 
 static void