if ((i >= tex->num_textures) || !tex->textures[i])
continue;
- enum pipe_format format = tex->textures[i]->format;
+ struct pipe_sampler_view *view = tex->textures[i];
+ enum pipe_format format = view->format;
const struct util_format_description *desc =
util_format_description(format);
e->rgb10a2 = 0;
e->z24 = 0;
+ unsigned char swiz[4];
+
+ fd6_tex_swiz(format, swiz,
+ view->swizzle_r, view->swizzle_g,
+ view->swizzle_b, view->swizzle_a);
+
for (j = 0; j < 4; j++) {
- int c = desc->swizzle[j];
+ int c = swiz[j];
int cd = c;
/*
static const struct fd6_pipe_sampler_view dummy_view = {};
const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
+ struct fd_resource *rsc = NULL;
+
+ if (view->base.texture)
+ rsc = fd_resource(view->base.texture);
OUT_RING(state, view->texconst0);
OUT_RING(state, view->texconst1);
OUT_RING(state, view->texconst2);
- OUT_RING(state, view->texconst3);
+ OUT_RING(state, view->texconst3 |
+ COND(rsc && view->ubwc_enabled,
+ A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
- if (view->base.texture) {
- struct fd_resource *rsc = fd_resource(view->base.texture);
+ if (rsc) {
if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
rsc = rsc->stencil;
- OUT_RELOC(state, rsc->bo, view->offset,
+ OUT_RELOC(state, rsc->bo, view->offset + rsc->offset,
(uint64_t)view->texconst5 << 32, 0);
} else {
OUT_RING(state, 0x00000000);
}
OUT_RING(state, view->texconst6);
- OUT_RING(state, view->texconst7);
- OUT_RING(state, view->texconst8);
+
+ if (rsc && view->ubwc_enabled) {
+ OUT_RELOC(state, rsc->bo, view->offset + rsc->ubwc_offset, 0, 0);
+ } else {
+ OUT_RING(state, 0);
+ OUT_RING(state, 0);
+ }
+
OUT_RING(state, view->texconst9);
OUT_RING(state, view->texconst10);
OUT_RING(state, view->texconst11);
struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
uint32_t i;
- for (i = 0; i < A6XX_MAX_RENDER_TARGETS; i++) {
+ for (i = 0; i < pfb->nr_cbufs; i++) {
enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
bool is_int = util_format_is_pure_integer(format);
bool has_alpha = util_format_has_alpha(format);
OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
- OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
- OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
- OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
- OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
- OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
-
OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
- OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000000);
-
OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
OUT_RING(ring, 0x00000000);