freedreno/a6xx: fix border-color swizzles

[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index f0e6e54785db54e16a0c280daf53b12eb0c8f77b..95ac616a76c39b7ba51d507e1e03cd91f049579b 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -196,7 +196,8 @@ setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entrie
                if ((i >= tex->num_textures) || !tex->textures[i])
                        continue;
 
-               enum pipe_format format = tex->textures[i]->format;
+               struct pipe_sampler_view *view = tex->textures[i];
+               enum pipe_format format = view->format;
                const struct util_format_description *desc =
                                util_format_description(format);
 
@@ -206,8 +207,14 @@ setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entrie
                e->rgb10a2 = 0;
                e->z24 = 0;
 
+               unsigned char swiz[4];
+
+               fd6_tex_swiz(format, swiz,
+                               view->swizzle_r, view->swizzle_g,
+                               view->swizzle_b, view->swizzle_a);
+
                for (j = 0; j < 4; j++) {
-                       int c = desc->swizzle[j];
+                       int c = swiz[j];
                        int cd = c;
 
                        /*
@@ -411,17 +418,22 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
                        static const struct fd6_pipe_sampler_view dummy_view = {};
                        const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
                                fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
+                       struct fd_resource *rsc = NULL;
+
+                       if (view->base.texture)
+                               rsc = fd_resource(view->base.texture);
 
                        OUT_RING(state, view->texconst0);
                        OUT_RING(state, view->texconst1);
                        OUT_RING(state, view->texconst2);
-                       OUT_RING(state, view->texconst3);
+                       OUT_RING(state, view->texconst3 |
+                               COND(rsc && view->ubwc_enabled,
+                                       A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_UNK27));
 
-                       if (view->base.texture) {
-                               struct fd_resource *rsc = fd_resource(view->base.texture);
+                       if (rsc) {
                                if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
                                        rsc = rsc->stencil;
-                               OUT_RELOC(state, rsc->bo, view->offset,
+                               OUT_RELOC(state, rsc->bo, view->offset + rsc->offset,
                                        (uint64_t)view->texconst5 << 32, 0);
                        } else {
                                OUT_RING(state, 0x00000000);
@@ -429,8 +441,14 @@ fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
                        }
 
                        OUT_RING(state, view->texconst6);
-                       OUT_RING(state, view->texconst7);
-                       OUT_RING(state, view->texconst8);
+
+                       if (rsc && view->ubwc_enabled) {
+                               OUT_RELOC(state, rsc->bo, view->offset + rsc->ubwc_offset, 0, 0);
+                       } else {
+                               OUT_RING(state, 0);
+                               OUT_RING(state, 0);
+                       }
+
                        OUT_RING(state, view->texconst9);
                        OUT_RING(state, view->texconst10);
                        OUT_RING(state, view->texconst11);
@@ -1175,47 +1193,9 @@ t7              opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
        OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
        OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
 
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
-       OUT_RING(ring, 0x00000000);   /* VPC_SO_BUFFER_BASE_LO_0 */
-       OUT_RING(ring, 0x00000000);   /* VPC_SO_BUFFER_BASE_HI_0 */
-       OUT_RING(ring, 0x00000000);   /* VPC_SO_BUFFER_SIZE_0 */
-
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
-       OUT_RING(ring, 0x00000000);   /* VPC_SO_FLUSH_BASE_LO_0 */
-       OUT_RING(ring, 0x00000000);   /* VPC_SO_FLUSH_BASE_HI_0 */
-
        OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
        OUT_RING(ring, 0x00000000);   /* VPC_SO_BUF_CNTL */
 
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
-       OUT_RING(ring, 0x00000000);   /* UNKNOWN_E2AB */
-
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-
-       OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-       OUT_RING(ring, 0x00000000);
-
        OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
        OUT_RING(ring, 0x00000000);