#include "util/format/u_format.h"
#include "freedreno_draw.h"
+#include "freedreno_log.h"
#include "freedreno_state.h"
#include "freedreno_resource.h"
OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
OUT_RING(ring,
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
+ A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
} else {
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
static void
emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
- struct fd_gmem_stateobj *gmem)
+ const struct fd_gmem_stateobj *gmem)
{
unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
unsigned srgb_cntl = 0;
unsigned i;
- bool layered = false;
- unsigned type = 0;
+ unsigned max_layer_index = 0;
for (i = 0; i < pfb->nr_cbufs; i++) {
- enum a6xx_color_fmt format = 0;
+ enum a6xx_format format = 0;
enum a3xx_color_swap swap = WZYX;
bool sint = false, uint = false;
struct fd_resource *rsc = NULL;
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
- stride = slice->pitch * rsc->layout.cpp;
+ stride = slice->pitch;
swap = fd6_resource_swap(rsc, pformat);
tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
-
- if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
- layered = true;
- if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
- type = LAYER_MULTISAMPLE_ARRAY;
- else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
- type = LAYER_2D_ARRAY;
- else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
- type = LAYER_CUBEMAP;
- else if (psurf->texture->target == PIPE_TEXTURE_3D)
- type = LAYER_3D;
- }
+ max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
.rt6 = mrt_comp[6],
.rt7 = mrt_comp[7]));
- OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
+ OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
}
static void
emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
- struct fd_gmem_stateobj *gmem)
+ const struct fd_gmem_stateobj *gmem)
{
if (zsbuf) {
struct fd_resource *rsc = fd_resource(zsbuf->texture);
enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
struct fdl_slice *slice = fd_resource_slice(rsc, 0);
- uint32_t stride = slice->pitch * rsc->layout.cpp;
+ uint32_t stride = slice->pitch;
uint32_t size = slice->size0;
uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
if (rsc->stencil) {
struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
- stride = slice->pitch * rsc->stencil->layout.cpp;
+ stride = slice->pitch;
size = slice->size0;
uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
}
} else {
- OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
- OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
+ OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
+ OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
static bool
use_hw_binning(struct fd_batch *batch)
{
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
// TODO figure out hw limits for binning
static void
patch_fb_read(struct fd_batch *batch)
{
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
cntl |= A6XX_RB_RENDER_CNTL_BINNING;
OUT_PKT7(ring, CP_REG_WRITE, 3);
- OUT_RING(ring, 0x2);
+ OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
OUT_RING(ring, cntl |
COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
{
struct fd_context *ctx = batch->ctx;
struct fd6_context *fd6_ctx = fd6_context(ctx);
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
int i;
OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
for (i = 0; i < 32; i++) {
- struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
+ const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
emit_vsc_overflow_test(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
emit_binning_pass(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
uint32_t x1 = gmem->minx;
A6XX_SP_TP_WINDOW_OFFSET_Y(0));
/* emit IB to binning drawcmds: */
+ fd_log(batch, "GMEM: START BINNING IB");
fd6_emit_ib(ring, batch->draw);
+ fd_log(batch, "GMEM: END BINNING IB");
fd_reset_wfi(batch);
OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
+ fd_log(batch, "START VSC OVERFLOW TEST");
emit_vsc_overflow_test(batch);
+ fd_log(batch, "END VSC OVERFLOW TEST");
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
OUT_RING(ring, 0x0);
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
fd6_emit_restore(batch, ring);
fd6_emit_lrz_flush(ring);
- if (batch->lrz_clear)
+ if (batch->lrz_clear) {
+ fd_log(batch, "START LRZ CLEAR");
fd6_emit_ib(ring, batch->lrz_clear);
+ fd_log(batch, "END LRZ CLEAR");
+ }
fd6_cache_inv(batch, ring);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
+ /* blob controls "local" in IB2, but I think that is not required */
+ OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
+
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
- emit_zs(ring, pfb->zsbuf, &ctx->gmem);
- emit_mrt(ring, pfb, &ctx->gmem);
+ emit_zs(ring, pfb->zsbuf, batch->gmem_state);
+ emit_mrt(ring, pfb, batch->gmem_state);
emit_msaa(ring, pfb->samples);
patch_fb_read(batch);
fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
emit_marker6(ring, 7);
uint32_t x1 = tile->xoff;
set_scissor(ring, x1, y1, x2, y2);
if (use_hw_binning(batch)) {
- struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
+ const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
set_window_offset(ring, x1, y1);
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
OUT_PKT7(ring, CP_SET_MODE, 1);
OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
- OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
- OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
- OUT_RING(ring, 0x0);
} else {
set_window_offset(ring, x1, y1);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
- enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
- uint32_t stride = slice->pitch * rsc->layout.cpp;
+ enum a6xx_format format = fd6_pipe2color(pfmt);
+ uint32_t stride = slice->pitch;
uint32_t size = slice->size0;
enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
enum a3xx_msaa_samples samples =
emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
uint32_t buffers = batch->fast_cleared;
break;
}
- if (util_format_is_pure_uint(pfmt)) {
- util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
- } else if (util_format_is_pure_sint(pfmt)) {
- util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
- } else {
- util_pack_color(swapped.f, pfmt, &uc);
- }
+ util_pack_color_union(pfmt, &uc, &swapped);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
+ A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
static void
emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
- struct fd_context *ctx = batch->ctx;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (batch->restore & FD_BUFFER_COLOR) {
static void
fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
{
+ fd_log(batch, "TILE: START CLEAR/RESTORE");
if (batch->fast_cleared || !use_hw_binning(batch)) {
fd6_emit_ib(batch->gmem, batch->tile_setup);
} else {
emit_conditional_ib(batch, tile, batch->tile_setup);
}
+ fd_log(batch, "TILE: END CLEAR/RESTORE");
}
static void
static void
prepare_tile_fini_ib(struct fd_batch *batch)
{
- struct fd_context *ctx = batch->ctx;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring;
/* if (no overflow) */ {
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
}
}
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
emit_marker6(ring, 7);
+ fd_log(batch, "TILE: START RESOLVE");
if (batch->fast_cleared || !use_hw_binning(batch)) {
fd6_emit_ib(batch->gmem, batch->tile_fini);
} else {
emit_conditional_ib(batch, tile, batch->tile_fini);
}
-
- OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
+ fd_log(batch, "TILE: END RESOLVE");
}
static void
}
}
- fd6_event_write(batch, ring, 0x1d, true);
+ fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
static void
fd6_emit_lrz_flush(ring);
+ if (batch->lrz_clear)
+ fd6_emit_ib(ring, batch->lrz_clear);
+
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
emit_marker6(ring, 7);
if (batch->tessellation)
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
+ /* blob controls "local" in IB2, but I think that is not required */
+ OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
+
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_cache_inv(batch, ring);
fd6_emit_lrz_flush(ring);
- fd6_event_write(batch, ring, UNK_1D, true);
+ fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
void
projects / mesa.git / blobdiff