#include "util/format/u_format.h"
#include "freedreno_draw.h"
+#include "freedreno_log.h"
#include "freedreno_state.h"
#include "freedreno_resource.h"
int level, int layer)
{
if (fd_resource_ubwc_enabled(rsc, level)) {
- OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
+ OUT_RELOC(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
OUT_RING(ring,
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
- A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
+ A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(fdl_ubwc_pitch(&rsc->layout, level)) |
+ A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
} else {
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
unsigned srgb_cntl = 0;
unsigned i;
- bool layered = false;
- unsigned type = 0;
+ unsigned max_layer_index = 0;
for (i = 0; i < pfb->nr_cbufs; i++) {
- enum a6xx_color_fmt format = 0;
+ enum a6xx_format format = 0;
enum a3xx_color_swap swap = WZYX;
bool sint = false, uint = false;
struct fd_resource *rsc = NULL;
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
- stride = slice->pitch * rsc->layout.cpp;
+ stride = fd_resource_pitch(rsc, psurf->u.tex.level);
swap = fd6_resource_swap(rsc, pformat);
tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
-
- if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
- layered = true;
- if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
- type = LAYER_MULTISAMPLE_ARRAY;
- else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
- type = LAYER_2D_ARRAY;
- else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
- type = LAYER_CUBEMAP;
- else if (psurf->texture->target == PIPE_TEXTURE_3D)
- type = LAYER_3D;
- }
+ max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
.rt6 = mrt_comp[6],
.rt7 = mrt_comp[7]));
- OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
+ OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
}
static void
if (zsbuf) {
struct fd_resource *rsc = fd_resource(zsbuf->texture);
enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
- struct fdl_slice *slice = fd_resource_slice(rsc, 0);
- uint32_t stride = slice->pitch * rsc->layout.cpp;
- uint32_t size = slice->size0;
+ uint32_t stride = fd_resource_pitch(rsc, 0);
+ uint32_t size = fd_resource_slice(rsc, 0)->size0;
uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
zsbuf->u.tex.first_layer);
OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
if (rsc->stencil) {
- struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
- stride = slice->pitch * rsc->stencil->layout.cpp;
- size = slice->size0;
+ stride = fd_resource_pitch(rsc->stencil, 0);
+ size = fd_resource_slice(rsc->stencil, 0)->size0;
uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
OUT_REG(ring,
OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
}
} else {
- OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
- OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
+ OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
+ OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
{
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
- // TODO figure out hw limits for binning
+ if ((gmem->maxpw * gmem->maxph) > 32)
+ return false;
return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
(batch->num_draws > 0);
cntl |= A6XX_RB_RENDER_CNTL_BINNING;
OUT_PKT7(ring, CP_REG_WRITE, 3);
- OUT_RING(ring, 0x2);
+ OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
OUT_RING(ring, cntl |
COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
}
-#define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
-#define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
+/* extra size to store VSC_DRAW_STRM_SIZE: */
+#define VSC_DRAW_STRM_SIZE(pitch) ((pitch) * 32 + 0x100)
+#define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
static void
update_vsc_pipe(struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->gmem;
int i;
+ if (batch->draw_strm_bits/8 > fd6_ctx->vsc_draw_strm_pitch) {
+ if (fd6_ctx->vsc_draw_strm)
+ fd_bo_del(fd6_ctx->vsc_draw_strm);
+ fd6_ctx->vsc_draw_strm = NULL;
+ /* Note: probably only need to align to 0x40, but aligning stronger
+ * reduces the odds that we will have to realloc again on the next
+ * frame:
+ */
+ fd6_ctx->vsc_draw_strm_pitch = align(batch->draw_strm_bits/8, 0x4000);
+ debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
+ fd6_ctx->vsc_draw_strm_pitch);
+ }
- if (!fd6_ctx->vsc_data) {
- fd6_ctx->vsc_data = fd_bo_new(ctx->screen->dev,
- VSC_DATA_SIZE(fd6_ctx->vsc_data_pitch),
- DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data");
+ if (batch->prim_strm_bits/8 > fd6_ctx->vsc_prim_strm_pitch) {
+ if (fd6_ctx->vsc_prim_strm)
+ fd_bo_del(fd6_ctx->vsc_prim_strm);
+ fd6_ctx->vsc_prim_strm = NULL;
+ fd6_ctx->vsc_prim_strm_pitch = align(batch->prim_strm_bits/8, 0x4000);
+ debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
+ fd6_ctx->vsc_prim_strm_pitch);
}
- if (!fd6_ctx->vsc_data2) {
- fd6_ctx->vsc_data2 = fd_bo_new(ctx->screen->dev,
- VSC_DATA2_SIZE(fd6_ctx->vsc_data2_pitch),
- DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data2");
+ if (!fd6_ctx->vsc_draw_strm) {
+ fd6_ctx->vsc_draw_strm = fd_bo_new(ctx->screen->dev,
+ VSC_DRAW_STRM_SIZE(fd6_ctx->vsc_draw_strm_pitch),
+ DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_draw_strm");
+ }
+
+ if (!fd6_ctx->vsc_prim_strm) {
+ fd6_ctx->vsc_prim_strm = fd_bo_new(ctx->screen->dev,
+ VSC_PRIM_STRM_SIZE(fd6_ctx->vsc_prim_strm_pitch),
+ DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_prim_strm");
}
OUT_REG(ring,
A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
- A6XX_VSC_SIZE_ADDRESS(.bo = fd6_ctx->vsc_data, .bo_offset = 32 * fd6_ctx->vsc_data_pitch));
+ A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
+ .bo = fd6_ctx->vsc_draw_strm,
+ .bo_offset = 32 * fd6_ctx->vsc_draw_strm_pitch));
OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
.ny = gmem->nbins_y));
}
OUT_REG(ring,
- A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = fd6_ctx->vsc_data2),
- A6XX_VSC_PIPE_DATA2_PITCH(.dword = fd6_ctx->vsc_data2_pitch),
- A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data2)));
+ A6XX_VSC_PRIM_STRM_ADDRESS(.bo = fd6_ctx->vsc_prim_strm),
+ A6XX_VSC_PRIM_STRM_PITCH(.dword = fd6_ctx->vsc_prim_strm_pitch),
+ A6XX_VSC_PRIM_STRM_LIMIT(.dword = fd6_ctx->vsc_prim_strm_pitch - 64));
OUT_REG(ring,
- A6XX_VSC_PIPE_DATA_ADDRESS(.bo = fd6_ctx->vsc_data),
- A6XX_VSC_PIPE_DATA_PITCH(.dword = fd6_ctx->vsc_data_pitch),
- A6XX_VSC_PIPE_DATA_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data)));
+ A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
+ A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
+ A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
}
-/* TODO we probably have more than 8 scratch regs.. although the first
- * 8 is what kernel dumps, and it is kinda useful to be able to see
- * the value in kernel traces
- */
-#define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
-
/*
- * If overflow is detected, either 0x1 (VSC_DATA overflow) or 0x3
- * (VSC_DATA2 overflow) plus the size of the overflowed buffer is
+ * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
+ * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
* written to control->vsc_overflow. This allows the CPU to
* detect which buffer overflowed (and, since the current size is
* encoded as well, this protects against already-submitted but
* not executed batches from fooling the CPU into increasing the
* size again unnecessarily).
- *
- * To conditionally use VSC data in draw pass only if there is no
- * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
- * if no overflow, or 0 in case of overflow. The value is inverted
- * to make the CP_COND_REG_EXEC stuff easier.
*/
static void
emit_vsc_overflow_test(struct fd_batch *batch)
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
- debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
- debug_assert((fd6_ctx->vsc_data2_pitch & 0x3) == 0);
-
- /* Clear vsc_scratch: */
- OUT_PKT7(ring, CP_MEM_WRITE, 3);
- OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
- OUT_RING(ring, 0x0);
+ debug_assert((fd6_ctx->vsc_draw_strm_pitch & 0x3) == 0);
+ debug_assert((fd6_ctx->vsc_prim_strm_pitch & 0x3) == 0);
/* Check for overflow, write vsc_scratch if detected: */
for (int i = 0; i < gmem->num_vsc_pipes; i++) {
OUT_PKT7(ring, CP_COND_WRITE5, 8);
OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
- OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
+ OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data_pitch));
+ OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch - 64));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
- OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
- OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_data_pitch));
+ OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
+ OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
OUT_PKT7(ring, CP_COND_WRITE5, 8);
OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
- OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
+ OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
- OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data2_pitch));
+ OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch - 64));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
- OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
- OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_data2_pitch));
+ OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
+ OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
}
OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
-
- OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
-
- OUT_PKT7(ring, CP_MEM_TO_REG, 3);
- OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
- CP_MEM_TO_REG_0_CNT(0));
- OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* SRC_LO/HI */
-
- /*
- * This is a bit awkward, we really want a way to invert the
- * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
- * execute cmds to use hwbinning when a bit is *not* set. This
- * dance is to invert OVERFLOW_FLAG_REG
- *
- * A CP_NOP packet is used to skip executing the 'else' clause
- * if (b0 set)..
- */
-
- BEGIN_RING(ring, 10); /* ensure if/else doesn't get split */
-
- /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
- OUT_PKT7(ring, CP_REG_TEST, 1);
- OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
-
- OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
- OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(7));
-
- /* if (b0 set) */ {
- /*
- * On overflow, mirror the value to control->vsc_overflow
- * which CPU is checking to detect overflow (see
- * check_vsc_overflow())
- */
- OUT_PKT7(ring, CP_REG_TO_MEM, 3);
- OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
- CP_REG_TO_MEM_0_CNT(1 - 1));
- OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
-
- OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
- OUT_RING(ring, 0x0);
-
- OUT_PKT7(ring, CP_NOP, 2); /* skip 'else' when 'if' is taken */
- } /* else */ {
- OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
- OUT_RING(ring, 0x1);
- }
}
static void
unsigned size = vsc_overflow & ~0x3;
if (buffer == 0x1) {
- /* VSC_PIPE_DATA overflow: */
+ /* VSC_DRAW_STRM overflow: */
- if (size < fd6_ctx->vsc_data_pitch) {
+ if (size < fd6_ctx->vsc_draw_strm_pitch) {
/* we've already increased the size, this overflow is
* from a batch submitted before resize, but executed
* after
return;
}
- fd_bo_del(fd6_ctx->vsc_data);
- fd6_ctx->vsc_data = NULL;
- fd6_ctx->vsc_data_pitch *= 2;
+ fd_bo_del(fd6_ctx->vsc_draw_strm);
+ fd6_ctx->vsc_draw_strm = NULL;
+ fd6_ctx->vsc_draw_strm_pitch *= 2;
- debug_printf("resized VSC_DATA_PITCH to: 0x%x\n", fd6_ctx->vsc_data_pitch);
+ debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
+ fd6_ctx->vsc_draw_strm_pitch);
} else if (buffer == 0x3) {
- /* VSC_PIPE_DATA2 overflow: */
+ /* VSC_PRIM_STRM overflow: */
- if (size < fd6_ctx->vsc_data2_pitch) {
+ if (size < fd6_ctx->vsc_prim_strm_pitch) {
/* we've already increased the size */
return;
}
- fd_bo_del(fd6_ctx->vsc_data2);
- fd6_ctx->vsc_data2 = NULL;
- fd6_ctx->vsc_data2_pitch *= 2;
+ fd_bo_del(fd6_ctx->vsc_prim_strm);
+ fd6_ctx->vsc_prim_strm = NULL;
+ fd6_ctx->vsc_prim_strm_pitch *= 2;
- debug_printf("resized VSC_DATA2_PITCH to: 0x%x\n", fd6_ctx->vsc_data2_pitch);
+ debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
+ fd6_ctx->vsc_prim_strm_pitch);
} else {
/* NOTE: it's possible, for example, for overflow to corrupt the
A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
OUT_REG(ring,
- A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
- A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
+ A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
+ A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
}
static void
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
- uint32_t x1 = gmem->minx;
- uint32_t y1 = gmem->miny;
- uint32_t x2 = gmem->minx + gmem->width - 1;
- uint32_t y2 = gmem->miny + gmem->height - 1;
-
debug_assert(!batch->tessellation);
- set_scissor(ring, x1, y1, x2, y2);
+ set_scissor(ring, 0, 0, gmem->width - 1, gmem->height - 1);
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
A6XX_SP_TP_WINDOW_OFFSET_Y(0));
/* emit IB to binning drawcmds: */
+ fd_log(batch, "GMEM: START BINNING IB");
fd6_emit_ib(ring, batch->draw);
+ fd_log(batch, "GMEM: END BINNING IB");
fd_reset_wfi(batch);
OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
+ fd_log(batch, "START VSC OVERFLOW TEST");
emit_vsc_overflow_test(batch);
+ fd_log(batch, "END VSC OVERFLOW TEST");
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
OUT_RING(ring, 0x0);
fd6_emit_lrz_flush(ring);
- if (batch->lrz_clear)
- fd6_emit_ib(ring, batch->lrz_clear);
+ if (batch->prologue) {
+ fd_log(batch, "START PROLOGUE");
+ fd6_emit_ib(ring, batch->prologue);
+ fd_log(batch, "END PROLOGUE");
+ }
fd6_cache_inv(batch, ring);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
+ /* blob controls "local" in IB2, but I think that is not required */
+ OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
+
fd_wfi(batch, ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
if (use_hw_binning(batch)) {
/* enable stream-out during binning pass: */
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, 0);
+ OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
set_bin_size(ring, gmem->bin_w, gmem->bin_h,
A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
emit_binning_pass(batch);
/* and disable stream-out for draw pass: */
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
+ OUT_REG(ring, A6XX_VPC_SO_DISABLE(true));
/*
* NOTE: even if we detect VSC overflow and disable use of
OUT_RING(ring, 0x1);
} else {
/* no binning pass, so enable stream-out for draw pass:: */
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, 0);
+ OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
}
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
emit_marker6(ring, 7);
uint32_t x1 = tile->xoff;
OUT_PKT7(ring, CP_SET_MODE, 1);
OUT_RING(ring, 0x0);
- /*
- * Conditionally execute if no VSC overflow:
- */
+ OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
+ OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
+ CP_SET_BIN_DATA5_0_VSC_N(tile->n));
+ OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
+ (tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
+ OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
+ (tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
+ OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
+ (tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
- BEGIN_RING(ring, 18); /* ensure if/else doesn't get split */
-
- OUT_PKT7(ring, CP_REG_TEST, 1);
- OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
-
- OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
- OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(11));
-
- /* if (no overflow) */ {
- OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
- OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
- CP_SET_BIN_DATA5_0_VSC_N(tile->n));
- OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
- (tile->p * fd6_ctx->vsc_data_pitch), 0, 0);
- OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
- (tile->p * 4) + (32 * fd6_ctx->vsc_data_pitch), 0, 0);
- OUT_RELOC(ring, fd6_ctx->vsc_data2,
- (tile->p * fd6_ctx->vsc_data2_pitch), 0, 0);
-
- OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
- OUT_RING(ring, 0x0);
-
- /* use a NOP packet to skip over the 'else' side: */
- OUT_PKT7(ring, CP_NOP, 2);
- } /* else */ {
- OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
- OUT_RING(ring, 0x1);
- }
+ OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
+ OUT_RING(ring, 0x0);
set_window_offset(ring, x1, y1);
OUT_PKT7(ring, CP_SET_MODE, 1);
OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
- OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
- OUT_RING(ring, 0x0);
-
- OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
- OUT_RING(ring, 0x0);
} else {
set_window_offset(ring, x1, y1);
static void
set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
- struct pipe_scissor_state blit_scissor;
- struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct pipe_scissor_state blit_scissor = batch->max_scissor;
- blit_scissor.minx = 0;
- blit_scissor.miny = 0;
- blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
- blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
+ blit_scissor.minx = ROUND_DOWN_TO(blit_scissor.minx, 16);
+ blit_scissor.miny = ROUND_DOWN_TO(blit_scissor.miny, 4);
+ blit_scissor.maxx = ALIGN(blit_scissor.maxx, 16);
+ blit_scissor.maxy = ALIGN(blit_scissor.maxy, 4);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring,
struct pipe_surface *psurf,
bool stencil)
{
- struct fdl_slice *slice;
struct fd_resource *rsc = fd_resource(psurf->texture);
enum pipe_format pfmt = psurf->format;
uint32_t offset;
pfmt = rsc->base.format;
}
- slice = fd_resource_slice(rsc, psurf->u.tex.level);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
- enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
- uint32_t stride = slice->pitch * rsc->layout.cpp;
- uint32_t size = slice->size0;
+ enum a6xx_format format = fd6_pipe2color(pfmt);
+ uint32_t stride = fd_resource_pitch(rsc, psurf->u.tex.level);
+ uint32_t size = fd_resource_slice(rsc, psurf->u.tex.level)->size0;
enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
enum a3xx_msaa_samples samples =
fd_msaa_samples(rsc->base.nr_samples);
break;
}
- if (util_format_is_pure_uint(pfmt)) {
- util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
- } else if (util_format_is_pure_sint(pfmt)) {
- util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
- } else {
- util_pack_color(swapped.f, pfmt, &uc);
- }
+ util_pack_color_union(pfmt, &uc, &swapped);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
- A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
+ A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
static void
fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
{
+ fd_log(batch, "TILE: START CLEAR/RESTORE");
if (batch->fast_cleared || !use_hw_binning(batch)) {
fd6_emit_ib(batch->gmem, batch->tile_setup);
} else {
emit_conditional_ib(batch, tile, batch->tile_setup);
}
+ fd_log(batch, "TILE: END CLEAR/RESTORE");
}
static void
} else {
emit_conditional_ib(batch, tile, batch->draw);
}
+
+ if (batch->epilogue)
+ fd6_emit_ib(batch->gmem, batch->epilogue);
}
static void
struct fd_ringbuffer *ring = batch->gmem;
if (use_hw_binning(batch)) {
- /* Conditionally execute if no VSC overflow: */
-
- BEGIN_RING(ring, 7); /* ensure if/else doesn't get split */
-
- OUT_PKT7(ring, CP_REG_TEST, 1);
- OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
- A6XX_CP_REG_TEST_0_BIT(0) |
- A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
-
- OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
- OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
- OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(2));
-
- /* if (no overflow) */ {
- OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
- }
+ OUT_PKT7(ring, CP_SET_MARKER, 1);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
}
OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
emit_marker6(ring, 7);
+ fd_log(batch, "TILE: START RESOLVE");
if (batch->fast_cleared || !use_hw_binning(batch)) {
fd6_emit_ib(batch->gmem, batch->tile_fini);
} else {
emit_conditional_ib(batch, tile, batch->tile_fini);
}
-
- OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
+ fd_log(batch, "TILE: END RESOLVE");
}
static void
struct fd_ringbuffer *ring = batch->gmem;
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
- OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
+ OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE);
fd6_emit_lrz_flush(ring);
- fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
+ fd6_event_write(batch, ring, PC_CCU_RESOLVE_TS, true);
if (use_hw_binning(batch)) {
check_vsc_overflow(batch->ctx);
value.ui[0] = batch->clear_stencil;
struct pipe_surface stencil_surf = *pfb->zsbuf;
+ stencil_surf.format = PIPE_FORMAT_S8_UINT;
stencil_surf.texture = separate_stencil;
fd6_clear_surface(ctx, ring,
}
}
- fd6_event_write(batch, ring, 0x1d, true);
+ fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
static void
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
- OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
+ OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
- OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
- OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
+ OUT_RELOC(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
+ OUT_RELOC(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
}
static void
struct fd_ringbuffer *ring = batch->gmem;
fd6_emit_restore(batch, ring);
+ fd6_emit_lrz_flush(ring);
+
+ if (batch->prologue) {
+ fd_log(batch, "START PROLOGUE");
+ fd6_emit_ib(ring, batch->prologue);
+ fd_log(batch, "END PROLOGUE");
+ }
if (pfb->width > 0 && pfb->height > 0)
set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
emit_sysmem_clears(batch, ring);
- fd6_emit_lrz_flush(ring);
-
emit_marker6(ring, 7);
OUT_PKT7(ring, CP_SET_MARKER, 1);
- OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
+ OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
emit_marker6(ring, 7);
if (batch->tessellation)
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
+ /* blob controls "local" in IB2, but I think that is not required */
+ OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
+ OUT_RING(ring, 0x1);
+
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_cache_inv(batch, ring);
OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
/* enable stream-out, with sysmem there is only one pass: */
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, 0);
+ OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
OUT_RING(ring, 0x1);
{
struct fd_ringbuffer *ring = batch->gmem;
+ if (batch->epilogue)
+ fd6_emit_ib(batch->gmem, batch->epilogue);
+
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x0);
fd6_emit_lrz_flush(ring);
- fd6_event_write(batch, ring, UNK_1D, true);
+ fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
void
projects / mesa.git / blobdiff