/* in layer_first layout, the level (slice) contains just one
* layer (since in fact the layer contains the slices)
*/
- uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size;
- int ta = rsc->cpp;
+ uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size;
+ int ta = rsc->layout.cpp;
/* The z16/r16 formats seem to not play by the normal tiling rules: */
- if ((rsc->cpp == 2) && (util_format_get_nr_components(format) == 1))
+ if ((rsc->layout.cpp == 2) && (util_format_get_nr_components(format) == 1))
ta = 0;
debug_assert(ta < ARRAY_SIZE(tile_alignment));
debug_assert(tile_alignment[ta].pitchalign);
for (level = 0; level <= prsc->last_level; level++) {
- struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
- bool linear_level = fd_resource_level_linear(prsc, level);
+ struct fdl_slice *slice = fd_resource_slice(rsc, level);
+ uint32_t tile_mode = fd_resource_tile_mode(prsc, level);
uint32_t width, height;
/* tiled levels of 3D textures are rounded up to PoT dimensions: */
- if ((prsc->target == PIPE_TEXTURE_3D) && rsc->tile_mode && !linear_level) {
+ if ((prsc->target == PIPE_TEXTURE_3D) && tile_mode) {
width = twidth;
height = theight;
} else {
uint32_t aligned_height = height;
uint32_t blocks;
- if (rsc->tile_mode && !linear_level) {
+ if (tile_mode) {
pitchalign = tile_alignment[ta].pitchalign;
aligned_height = align(aligned_height,
tile_alignment[ta].heightalign);
* range gets into range, we stop reducing it.
*/
if (prsc->target == PIPE_TEXTURE_3D) {
- if (level <= 1 || (rsc->slices[level - 1].size0 > 0xf000)) {
- slice->size0 = align(blocks * rsc->cpp, alignment);
+ if (level < 1 || fd_resource_slice(rsc, level - 1)->size0 > 0xf000) {
+ slice->size0 = align(blocks * rsc->layout.cpp, alignment);
} else {
- slice->size0 = rsc->slices[level - 1].size0;
+ slice->size0 = fd_resource_slice(rsc, level - 1)->size0;
}
} else {
- slice->size0 = align(blocks * rsc->cpp, alignment);
+ slice->size0 = align(blocks * rsc->layout.cpp, alignment);
}
size += slice->size0 * depth * layers_in_level;
#if 0
- debug_printf("%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u\n",
+ fprintf(stderr, "%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x tiling=%d\n",
util_format_name(prsc->format),
- width, height, depth, rsc->cpp,
- level, slice->pitch * rsc->cpp,
- slice->size0, size, aligned_height, blocks);
+ width, height, depth, rsc->layout.cpp,
+ level, slice->pitch * rsc->layout.cpp,
+ slice->size0, size, aligned_height, blocks,
+ slice->offset, fd_resource_tile_mode(prsc, level));
#endif
depth = u_minify(depth, 1);
* it can be tiled doesn't mean it can be compressed.
*/
static bool
-ok_ubwc_format(enum a6xx_color_fmt fmt)
+ok_ubwc_format(enum pipe_format pfmt)
{
- switch (fmt) {
+ /* NOTE: both x24s8 and z24s8 map to RB6_X8Z24_UNORM, but UBWC
+ * does not seem to work properly when sampling x24s8.. possibly
+ * because we sample it as TFMT6_8_8_8_8_UINT.
+ *
+ * This could possibly be a hw limitation, or maybe something
+ * else wrong somewhere (although z24s8 blits and sampling with
+ * UBWC seem fine). Recheck on a later revision of a6xx
+ */
+ if (pfmt == PIPE_FORMAT_X24S8_UINT)
+ return false;
+
+ switch (fd6_pipe2color(pfmt)) {
case RB6_R10G10B10A2_UINT:
case RB6_R10G10B10A2_UNORM:
case RB6_R11G11B10_FLOAT:
case RB6_R32G32B32A32_UINT:
case RB6_R32G32_SINT:
case RB6_R32G32_UINT:
- case RB6_R32_SINT:
- case RB6_R32_UINT:
case RB6_R5G6B5_UNORM:
case RB6_R8G8B8A8_SINT:
case RB6_R8G8B8A8_UINT:
case RB6_R8G8_SINT:
case RB6_R8G8_UINT:
case RB6_R8G8_UNORM:
- case RB6_X8Z24_UNORM:
+ case RB6_Z24_UNORM_S8_UINT:
+ case RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8:
return true;
default:
return false;
uint32_t width = prsc->width0;
uint32_t height = prsc->height0;
- if (!ok_ubwc_format(fd6_pipe2color(prsc->format)))
+ if (!ok_ubwc_format(prsc->format))
return 0;
/* limit things to simple single level 2d for now: */
return 0;
uint32_t block_width, block_height;
- switch (rsc->cpp) {
+ switch (rsc->layout.cpp) {
case 2:
case 4:
block_width = 16;
* because it is what the kernel expects for scanout. For non-2D we
* could just use a separate UBWC buffer..
*/
- rsc->ubwc_offset = 0;
- rsc->offset = meta_size;
- rsc->ubwc_pitch = meta_stride;
- rsc->ubwc_size = meta_size >> 2; /* in dwords??? */
- rsc->tile_mode = TILE6_3;
+ rsc->layout.ubwc_offset = 0;
+ rsc->layout.offset = meta_size;
+ rsc->layout.ubwc_pitch = meta_stride;
+ rsc->layout.ubwc_size = meta_size >> 2; /* in dwords??? */
+ rsc->layout.tile_mode = TILE6_3;
return meta_size;
}
+/**
+ * Ensure the rsc is in an ok state to be used with the specified format.
+ * This handles the case of UBWC buffers used with non-UBWC compatible
+ * formats, by triggering an uncompress.
+ */
+void
+fd6_validate_format(struct fd_context *ctx, struct fd_resource *rsc,
+ enum pipe_format format)
+{
+ if (!rsc->layout.ubwc_size)
+ return;
+
+ if (ok_ubwc_format(format))
+ return;
+
+ fd_resource_uncompress(ctx, rsc);
+}
+
uint32_t
fd6_setup_slices(struct fd_resource *rsc)
{
switch (rsc->base.target) {
case PIPE_TEXTURE_3D:
- rsc->layer_first = false;
+ rsc->layout.layer_first = false;
alignment = 4096;
break;
default:
- rsc->layer_first = true;
+ rsc->layout.layer_first = true;
alignment = 1;
break;
}
projects / mesa.git / blobdiff