freedreno: track batch/blit types

[mesa.git] / src / gallium / drivers / freedreno / adreno_common.xml.h

diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h
index 9d767d2446dcdbd4871fc425f728555ad56c166b..1f18fc6fc14ae5fdbfc24ffb04e5e083674f5073 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_common.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_common.xml.h
@@ -8,16 +8,18 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   9859 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14960 bytes, from 2014-07-27 17:22:13)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  60542 bytes, from 2014-09-27 15:55:28)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  41068 bytes, from 2014-08-01 12:22:48)
-
-Copyright (C) 2013-2014 by the following authors:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2016-02-10 17:07:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2016-02-10 21:03:25)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  16185 bytes, from 2016-03-05 03:08:05)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  83967 bytes, from 2016-02-10 17:07:21)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          ( 110685 bytes, from 2016-04-25 17:56:43)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
+
+Copyright (C) 2013-2016 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 
 Permission is hereby granted, free of charge, to any person obtaining
 a copy of this software and associated documentation files (the
@@ -85,6 +87,10 @@ enum adreno_rb_blend_factor {
        FACTOR_CONSTANT_ALPHA = 14,
        FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
        FACTOR_SRC_ALPHA_SATURATE = 16,
+       FACTOR_SRC1_COLOR = 20,
+       FACTOR_ONE_MINUS_SRC1_COLOR = 21,
+       FACTOR_SRC1_ALPHA = 22,
+       FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
 };
 
 enum adreno_rb_surface_endian {
@@ -105,6 +111,7 @@ enum adreno_rb_dither_mode {
 enum adreno_rb_depth_format {
        DEPTHX_16 = 0,
        DEPTHX_24_8 = 1,
+       DEPTHX_32 = 2,
 };
 
 enum adreno_rb_copy_control_mode {
@@ -113,6 +120,25 @@ enum adreno_rb_copy_control_mode {
        RB_COPY_DEPTH_STENCIL = 5,
 };
 
+enum a3xx_rop_code {
+       ROP_CLEAR = 0,
+       ROP_NOR = 1,
+       ROP_AND_INVERTED = 2,
+       ROP_COPY_INVERTED = 3,
+       ROP_AND_REVERSE = 4,
+       ROP_INVERT = 5,
+       ROP_XOR = 6,
+       ROP_NAND = 7,
+       ROP_AND = 8,
+       ROP_EQUIV = 9,
+       ROP_NOOP = 10,
+       ROP_OR_INVERTED = 11,
+       ROP_COPY = 12,
+       ROP_OR_REVERSE = 13,
+       ROP_OR = 14,
+       ROP_SET = 15,
+};
+
 enum a3xx_render_mode {
        RB_RENDERING_PASS = 0,
        RB_TILING_PASS = 1,
@@ -132,6 +158,7 @@ enum a3xx_threadmode {
 };
 
 enum a3xx_instrbuffermode {
+       CACHE = 0,
        BUFFER = 1,
 };
 
@@ -140,6 +167,13 @@ enum a3xx_threadsize {
        FOUR_QUADS = 1,
 };
 
+enum a3xx_color_swap {
+       WZYX = 0,
+       WXYZ = 1,
+       ZYXW = 2,
+       XYZW = 3,
+};
+
 #define REG_AXXX_CP_RB_BASE                                    0x000001c0
 
 #define REG_AXXX_CP_RB_CNTL                                    0x000001c1