u_upload_mgr: allow specifying PIPE_USAGE_* for the upload buffer

[mesa.git] / src / gallium / drivers / freedreno / adreno_common.xml.h

diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h
index d152dff36fd759b77eaa690a43df1f954b564ca6..f9c0e6aaa83116bcc2c94e6280f1f4b93ce6bcad 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_common.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_common.xml.h
@@ -8,15 +8,16 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32840 bytes, from 2014-01-05 14:44:21)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   8900 bytes, from 2014-01-05 14:44:21)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  12362 bytes, from 2014-01-07 14:47:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  54368 bytes, from 2014-01-05 14:44:21)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (   8344 bytes, from 2013-11-30 14:49:47)
-
-Copyright (C) 2013-2014 by the following authors:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2015-11-24 14:39:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15149 bytes, from 2015-11-20 16:22:25)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  69600 bytes, from 2015-11-24 14:39:00)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  67220 bytes, from 2015-12-13 17:58:09)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
+
+Copyright (C) 2013-2015 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 
 Permission is hereby granted, free of charge, to any person obtaining
@@ -85,15 +86,10 @@ enum adreno_rb_blend_factor {
        FACTOR_CONSTANT_ALPHA = 14,
        FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
        FACTOR_SRC_ALPHA_SATURATE = 16,
-};
-
-enum adreno_rb_blend_opcode {
-       BLEND_DST_PLUS_SRC = 0,
-       BLEND_SRC_MINUS_DST = 1,
-       BLEND_MIN_DST_SRC = 2,
-       BLEND_MAX_DST_SRC = 3,
-       BLEND_DST_MINUS_SRC = 4,
-       BLEND_DST_PLUS_SRC_BIAS = 5,
+       FACTOR_SRC1_COLOR = 20,
+       FACTOR_ONE_MINUS_SRC1_COLOR = 21,
+       FACTOR_SRC1_ALPHA = 22,
+       FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
 };
 
 enum adreno_rb_surface_endian {
@@ -114,6 +110,67 @@ enum adreno_rb_dither_mode {
 enum adreno_rb_depth_format {
        DEPTHX_16 = 0,
        DEPTHX_24_8 = 1,
+       DEPTHX_32 = 2,
+};
+
+enum adreno_rb_copy_control_mode {
+       RB_COPY_RESOLVE = 1,
+       RB_COPY_CLEAR = 2,
+       RB_COPY_DEPTH_STENCIL = 5,
+};
+
+enum a3xx_rop_code {
+       ROP_CLEAR = 0,
+       ROP_NOR = 1,
+       ROP_AND_INVERTED = 2,
+       ROP_COPY_INVERTED = 3,
+       ROP_AND_REVERSE = 4,
+       ROP_INVERT = 5,
+       ROP_XOR = 6,
+       ROP_NAND = 7,
+       ROP_AND = 8,
+       ROP_EQUIV = 9,
+       ROP_NOOP = 10,
+       ROP_OR_INVERTED = 11,
+       ROP_COPY = 12,
+       ROP_OR_REVERSE = 13,
+       ROP_OR = 14,
+       ROP_SET = 15,
+};
+
+enum a3xx_render_mode {
+       RB_RENDERING_PASS = 0,
+       RB_TILING_PASS = 1,
+       RB_RESOLVE_PASS = 2,
+       RB_COMPUTE_PASS = 3,
+};
+
+enum a3xx_msaa_samples {
+       MSAA_ONE = 0,
+       MSAA_TWO = 1,
+       MSAA_FOUR = 2,
+};
+
+enum a3xx_threadmode {
+       MULTI = 0,
+       SINGLE = 1,
+};
+
+enum a3xx_instrbuffermode {
+       CACHE = 0,
+       BUFFER = 1,
+};
+
+enum a3xx_threadsize {
+       TWO_QUADS = 0,
+       FOUR_QUADS = 1,
+};
+
+enum a3xx_color_swap {
+       WZYX = 0,
+       WXYZ = 1,
+       ZYXW = 2,
+       XYZW = 3,
 };
 
 #define REG_AXXX_CP_RB_BASE                                    0x000001c0
@@ -264,6 +321,8 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
 #define REG_AXXX_CP_INT_ACK                                    0x000001f4
 
 #define REG_AXXX_CP_ME_CNTL                                    0x000001f6
+#define AXXX_CP_ME_CNTL_BUSY                                   0x20000000
+#define AXXX_CP_ME_CNTL_HALT                                   0x10000000
 
 #define REG_AXXX_CP_ME_STATUS                                  0x000001f7