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freedreno/ir3: fix sam argument order comment
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
index cfc6ccbe8b3ff1a80d06430e0ca31bc99af23d4a..05afc66ee8b10389f368c34c50ce7443dc4d20c9 100644 (file)
--- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h
+++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h
@@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are:
 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    364 bytes, from 2013-11-30 14:47:15)
 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2013-03-31 16:51:27)
 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2014-06-02 15:21:30)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10347 bytes, from 2014-10-01 18:55:57)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  14960 bytes, from 2014-07-27 17:22:13)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  60542 bytes, from 2014-10-01 18:56:14)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  41068 bytes, from 2014-08-01 12:22:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  10551 bytes, from 2014-11-13 22:44:30)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15085 bytes, from 2014-12-20 21:49:41)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  64771 bytes, from 2015-03-15 21:55:57)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  51942 bytes, from 2015-02-24 17:14:02)
 
 Copyright (C) 2013-2014 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
@@ -157,6 +157,7 @@ enum adreno_pm4_type3_packets {
        CP_IM_STORE = 44,
        CP_SET_DRAW_INIT_FLAGS = 75,
        CP_SET_PROTECTED_MODE = 95,
+       CP_BOOTSTRAP_UCODE = 111,
        CP_LOAD_STATE = 48,
        CP_COND_INDIRECT_BUFFER_PFE = 58,
        CP_COND_INDIRECT_BUFFER_PFD = 50,
@@ -171,7 +172,9 @@ enum adreno_pm4_type3_packets {
        CP_DRAW_INDIRECT = 40,
        CP_DRAW_INDX_INDIRECT = 41,
        CP_DRAW_AUTO = 36,
+       CP_UNKNOWN_19 = 25,
        CP_UNKNOWN_1A = 26,
+       CP_UNKNOWN_4E = 78,
        CP_WIDE_REG_WRITE = 116,
        IN_IB_PREFETCH_END = 23,
        IN_SUBBLK_PREFETCH = 31,
@@ -202,6 +205,12 @@ enum adreno_state_src {
        SS_INDIRECT = 4,
 };
 
+enum a4xx_index_size {
+       INDEX4_SIZE_8_BIT = 0,
+       INDEX4_SIZE_16_BIT = 1,
+       INDEX4_SIZE_32_BIT = 2,
+};
+
 #define REG_CP_LOAD_STATE_0                                    0x00000000
 #define CP_LOAD_STATE_0_DST_OFF__MASK                          0x0000ffff
 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                         0
@@ -278,11 +287,11 @@ static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 #define CP_DRAW_INDX_1_NOT_EOP                                 0x00001000
 #define CP_DRAW_INDX_1_SMALL_INDEX                             0x00002000
 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE               0x00004000
-#define CP_DRAW_INDX_1_NUM_INDICES__MASK                       0xffff0000
-#define CP_DRAW_INDX_1_NUM_INDICES__SHIFT                      16
-static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
+#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                     0xff000000
+#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                    24
+static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
+       return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 }
 
 #define REG_CP_DRAW_INDX_2                                     0x00000002
@@ -293,20 +302,20 @@ static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
        return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 }
 
-#define REG_CP_DRAW_INDX_2                                     0x00000002
-#define CP_DRAW_INDX_2_INDX_BASE__MASK                         0xffffffff
-#define CP_DRAW_INDX_2_INDX_BASE__SHIFT                                0
-static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
+#define REG_CP_DRAW_INDX_3                                     0x00000003
+#define CP_DRAW_INDX_3_INDX_BASE__MASK                         0xffffffff
+#define CP_DRAW_INDX_3_INDX_BASE__SHIFT                                0
+static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
+       return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 }
 
-#define REG_CP_DRAW_INDX_2                                     0x00000002
-#define CP_DRAW_INDX_2_INDX_SIZE__MASK                         0xffffffff
-#define CP_DRAW_INDX_2_INDX_SIZE__SHIFT                                0
-static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
+#define REG_CP_DRAW_INDX_4                                     0x00000004
+#define CP_DRAW_INDX_4_INDX_SIZE__MASK                         0xffffffff
+#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                                0
+static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
+       return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 }
 
 #define REG_CP_DRAW_INDX_2_0                                   0x00000000
@@ -345,11 +354,11 @@ static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 #define CP_DRAW_INDX_2_1_NOT_EOP                               0x00001000
 #define CP_DRAW_INDX_2_1_SMALL_INDEX                           0x00002000
 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE             0x00004000
-#define CP_DRAW_INDX_2_1_NUM_INDICES__MASK                     0xffff0000
-#define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT                    16
-static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
+#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                   0xff000000
+#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                  24
+static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
+       return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 }
 
 #define REG_CP_DRAW_INDX_2_2                                   0x00000002
@@ -373,29 +382,20 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 }
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK                   0x00000700
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT                  8
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
-       return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                 0x00000800
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                        11
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                 0x00000c00
+#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                        10
+static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 {
        return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 }
-#define CP_DRAW_INDX_OFFSET_0_NOT_EOP                          0x00001000
-#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX                      0x00002000
-#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE                0x00004000
-#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK                        0xffff0000
-#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT               16
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
-{
-       return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
-}
 
 #define REG_CP_DRAW_INDX_OFFSET_1                              0x00000001
+#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK              0xffffffff
+#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT             0
+static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
+{
+       return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
+}
 
 #define REG_CP_DRAW_INDX_OFFSET_2                              0x00000002
 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                        0xffffffff
@@ -405,20 +405,22 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
        return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 }
 
-#define REG_CP_DRAW_INDX_OFFSET_2                              0x00000002
-#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK                  0xffffffff
-#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT                 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
+#define REG_CP_DRAW_INDX_OFFSET_3                              0x00000003
+
+#define REG_CP_DRAW_INDX_OFFSET_4                              0x00000004
+#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                  0xffffffff
+#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                 0
+static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
+       return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 }
 
-#define REG_CP_DRAW_INDX_OFFSET_2                              0x00000002
-#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK                  0xffffffff
-#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT                 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
+#define REG_CP_DRAW_INDX_OFFSET_5                              0x00000005
+#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                  0xffffffff
+#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                 0
+static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 {
-       return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
+       return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 }
 
 #define REG_CP_SET_DRAW_STATE_0                                        0x00000000