freedreno/ir3: fix sam argument order comment
[mesa.git] / src / gallium / drivers / freedreno / freedreno_draw.h
index 2a4fe06e3004c7d5f2c41608a726518f4e0b3ed9..3224fb14652336f5e34b2c00c74bcbeca0b10c89 100644 (file)
 #include "pipe/p_context.h"
 
 #include "freedreno_context.h"
+#include "freedreno_resource.h"
 #include "freedreno_screen.h"
 #include "freedreno_util.h"
 
 struct fd_ringbuffer;
 
-void fd_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
-               enum pc_di_vis_cull_mode vismode,
-               const struct pipe_draw_info *info);
-
 void fd_draw_init(struct pipe_context *pctx);
 
 static inline void
@@ -49,6 +46,7 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
                enum pc_di_primtype primtype,
                enum pc_di_vis_cull_mode vismode,
                enum pc_di_src_sel src_sel, uint32_t count,
+               uint8_t instances,
                enum pc_di_index_size idx_type,
                uint32_t idx_size, uint32_t idx_offset,
                struct fd_bo *idx_bo)
@@ -66,7 +64,7 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_PKT3(ring, CP_DRAW_INDX, 3);
                OUT_RING(ring, 0x00000000);
                OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
-                               INDEX_SIZE_IGN, USE_VISIBILITY));
+                                                       INDEX_SIZE_IGN, USE_VISIBILITY, 0));
                OUT_RING(ring, 0);             /* NumIndices */
 
                /* ugg, hard-code register offset to avoid pulling in the
@@ -82,10 +80,10 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
                /* leave vis mode blank for now, it will be patched up when
                 * we know if we are binning or not
                 */
-               OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0),
+               OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0, instances),
                                &ctx->draw_patches);
        } else {
-               OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode));
+               OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances));
        }
        OUT_RING(ring, count);             /* NumIndices */
        if (idx_bo) {
@@ -98,4 +96,52 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
        fd_reset_wfi(ctx);
 }
 
+
+static inline enum pc_di_index_size
+size2indextype(unsigned index_size)
+{
+       switch (index_size) {
+       case 1: return INDEX_SIZE_8_BIT;
+       case 2: return INDEX_SIZE_16_BIT;
+       case 4: return INDEX_SIZE_32_BIT;
+       }
+       DBG("unsupported index size: %d", index_size);
+       assert(0);
+       return INDEX_SIZE_IGN;
+}
+
+/* this is same for a2xx/a3xx, so split into helper: */
+static inline void
+fd_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
+               enum pc_di_primtype primtype,
+               enum pc_di_vis_cull_mode vismode,
+               const struct pipe_draw_info *info)
+{
+       struct pipe_index_buffer *idx = &ctx->indexbuf;
+       struct fd_bo *idx_bo = NULL;
+       enum pc_di_index_size idx_type = INDEX_SIZE_IGN;
+       enum pc_di_src_sel src_sel;
+       uint32_t idx_size, idx_offset;
+
+       if (info->indexed) {
+               assert(!idx->user_buffer);
+
+               idx_bo = fd_resource(idx->buffer)->bo;
+               idx_type = size2indextype(idx->index_size);
+               idx_size = idx->index_size * info->count;
+               idx_offset = idx->offset + (info->start * idx->index_size);
+               src_sel = DI_SRC_SEL_DMA;
+       } else {
+               idx_bo = NULL;
+               idx_type = INDEX_SIZE_IGN;
+               idx_size = 0;
+               idx_offset = 0;
+               src_sel = DI_SRC_SEL_AUTO_INDEX;
+       }
+
+       fd_draw(ctx, ring, primtype, vismode, src_sel,
+                       info->count, info->instance_count - 1,
+                       idx_type, idx_size, idx_offset, idx_bo);
+}
+
 #endif /* FREEDRENO_DRAW_H_ */