freedreno/a5xx: bordercolor fixes

[mesa.git] / src / gallium / drivers / freedreno / freedreno_draw.h

diff --git a/src/gallium/drivers/freedreno/freedreno_draw.h b/src/gallium/drivers/freedreno/freedreno_draw.h
index 2a4fe06e3004c7d5f2c41608a726518f4e0b3ed9..b293f73b82ed4f4f89f037df3d7f5d084d97db9b 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_draw.h
+++ b/src/gallium/drivers/freedreno/freedreno_draw.h
@@ -33,25 +33,23 @@
 #include "pipe/p_context.h"
 
 #include "freedreno_context.h"
+#include "freedreno_resource.h"
 #include "freedreno_screen.h"
 #include "freedreno_util.h"
 
 struct fd_ringbuffer;
 
-void fd_draw_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
-               enum pc_di_vis_cull_mode vismode,
-               const struct pipe_draw_info *info);
-
 void fd_draw_init(struct pipe_context *pctx);
 
 static inline void
-fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
+fd_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
                enum pc_di_primtype primtype,
                enum pc_di_vis_cull_mode vismode,
                enum pc_di_src_sel src_sel, uint32_t count,
+               uint8_t instances,
                enum pc_di_index_size idx_type,
                uint32_t idx_size, uint32_t idx_offset,
-               struct fd_bo *idx_bo)
+               struct pipe_resource *idx_buffer)
 {
        /* for debug after a lock up, write a unique counter value
         * to scratch7 for each draw, to make it easier to match up
@@ -61,12 +59,12 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
         */
        emit_marker(ring, 7);
 
-       if (is_a3xx_p0(ctx->screen)) {
+       if (is_a3xx_p0(batch->ctx->screen)) {
                /* dummy-draw workaround: */
                OUT_PKT3(ring, CP_DRAW_INDX, 3);
                OUT_RING(ring, 0x00000000);
                OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
-                               INDEX_SIZE_IGN, USE_VISIBILITY));
+                                                       INDEX_SIZE_IGN, USE_VISIBILITY, 0));
                OUT_RING(ring, 0);             /* NumIndices */
 
                /* ugg, hard-code register offset to avoid pulling in the
@@ -76,26 +74,74 @@ fd_draw(struct fd_context *ctx, struct fd_ringbuffer *ring,
                OUT_RING(ring, 0);
        }
 
-       OUT_PKT3(ring, CP_DRAW_INDX, idx_bo ? 5 : 3);
+       OUT_PKT3(ring, CP_DRAW_INDX, idx_buffer ? 5 : 3);
        OUT_RING(ring, 0x00000000);        /* viz query info. */
        if (vismode == USE_VISIBILITY) {
                /* leave vis mode blank for now, it will be patched up when
                 * we know if we are binning or not
                 */
-               OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0),
-                               &ctx->draw_patches);
+               OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0, instances),
+                               &batch->draw_patches);
        } else {
-               OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode));
+               OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances));
        }
        OUT_RING(ring, count);             /* NumIndices */
-       if (idx_bo) {
-               OUT_RELOC(ring, idx_bo, idx_offset, 0, 0);
+       if (idx_buffer) {
+               OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
                OUT_RING (ring, idx_size);
        }
 
        emit_marker(ring, 7);
 
-       fd_reset_wfi(ctx);
+       fd_reset_wfi(batch);
+}
+
+
+static inline enum pc_di_index_size
+size2indextype(unsigned index_size)
+{
+       switch (index_size) {
+       case 1: return INDEX_SIZE_8_BIT;
+       case 2: return INDEX_SIZE_16_BIT;
+       case 4: return INDEX_SIZE_32_BIT;
+       }
+       DBG("unsupported index size: %d", index_size);
+       assert(0);
+       return INDEX_SIZE_IGN;
+}
+
+/* this is same for a2xx/a3xx, so split into helper: */
+static inline void
+fd_draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
+               enum pc_di_primtype primtype,
+               enum pc_di_vis_cull_mode vismode,
+               const struct pipe_draw_info *info,
+               unsigned index_offset)
+{
+       struct pipe_resource *idx_buffer = NULL;
+       enum pc_di_index_size idx_type = INDEX_SIZE_IGN;
+       enum pc_di_src_sel src_sel;
+       uint32_t idx_size, idx_offset;
+
+       if (info->index_size) {
+               assert(!info->has_user_indices);
+
+               idx_buffer = info->index.resource;
+               idx_type = size2indextype(info->index_size);
+               idx_size = info->index_size * info->count;
+               idx_offset = index_offset + info->start * info->index_size;
+               src_sel = DI_SRC_SEL_DMA;
+       } else {
+               idx_buffer = NULL;
+               idx_type = INDEX_SIZE_IGN;
+               idx_size = 0;
+               idx_offset = 0;
+               src_sel = DI_SRC_SEL_AUTO_INDEX;
+       }
+
+       fd_draw(batch, ring, primtype, vismode, src_sel,
+                       info->count, info->instance_count - 1,
+                       idx_type, idx_size, idx_offset, idx_buffer);
 }
 
 #endif /* FREEDRENO_DRAW_H_ */