-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
/*
* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
*
#include "util/u_string.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
-#include "util/u_pack_color.h"
+#include "util/u_format.h"
#include "freedreno_gmem.h"
#include "freedreno_context.h"
-#include "freedreno_state.h"
-#include "freedreno_program.h"
+#include "freedreno_fence.h"
#include "freedreno_resource.h"
-#include "freedreno_zsa.h"
+#include "freedreno_query_hw.h"
#include "freedreno_util.h"
/*
* resolve.
*/
-static uint32_t fmt2swap(enum pipe_format format)
+static uint32_t bin_width(struct fd_screen *screen)
{
- switch (format) {
- case PIPE_FORMAT_B8G8R8A8_UNORM:
- /* TODO probably some more.. */
- return 1;
- default:
- return 0;
- }
+ if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
+ return 1024;
+ if (is_a3xx(screen))
+ return 992;
+ return 512;
}
-/* transfer from gmem to system memory (ie. normal RAM) */
-
-static void
-emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t base,
- struct pipe_surface *psurf)
+static uint32_t
+total_size(uint8_t cbuf_cpp[], uint8_t zsbuf_cpp[2],
+ uint32_t bin_w, uint32_t bin_h, uint32_t gmem_align,
+ struct fd_gmem_stateobj *gmem)
{
- struct fd_resource *rsc = fd_resource(psurf->texture);
- uint32_t swap = fmt2swap(psurf->format);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
- OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
- A2XX_RB_COLOR_INFO_BASE(base / 1024) |
- A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 5);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
- OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
- OUT_RELOC(ring, rsc->bo, 0, 0); /* RB_COPY_DEST_BASE */
- OUT_RING(ring, rsc->pitch >> 5); /* RB_COPY_DEST_PITCH */
- OUT_RING(ring, /* RB_COPY_DEST_INFO */
- A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
- A2XX_RB_COPY_DEST_INFO_LINEAR |
- A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
- A2XX_RB_COPY_DEST_INFO_WRITE_RED |
- A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
- A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
- A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
-
- OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
- OUT_RING(ring, 0x0000000);
-
- OUT_PKT3(ring, CP_DRAW_INDX, 3);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
- INDEX_SIZE_IGN, IGNORE_VISIBILITY));
- OUT_RING(ring, 3); /* NumIndices */
-}
+ uint32_t total = 0, i;
-static void
-emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
- uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
-{
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-
- fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
- { .prsc = ctx->solid_vertexbuf, .size = 48 },
- }, 1);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
- OUT_RING(ring, 0);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
- OUT_RING(ring, 0x0000028f);
-
- fd_program_emit(ring, &ctx->solid_prog);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
- OUT_RING(ring, 0x0000ffff);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
- OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
- OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
- A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
- A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 3);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
- OUT_RING(ring, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
- OUT_RING(ring, xy2d(pfb->width, pfb->height)); /* PA_SC_WINDOW_SCISSOR_BR */
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
- OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
- A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
- OUT_RING(ring, 0x00000000);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
- OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
- OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(xoff) |
- A2XX_RB_COPY_DEST_OFFSET_Y(yoff));
-
- if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
- emit_gmem2mem_surf(ring, bin_w * bin_h, pfb->zsbuf);
-
- if (ctx->resolve & FD_BUFFER_COLOR)
- emit_gmem2mem_surf(ring, 0, pfb->cbufs[0]);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
- OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
-}
+ for (i = 0; i < MAX_RENDER_TARGETS; i++) {
+ if (cbuf_cpp[i]) {
+ gmem->cbuf_base[i] = align(total, gmem_align);
+ total = gmem->cbuf_base[i] + cbuf_cpp[i] * bin_w * bin_h;
+ }
+ }
-/* transfer from system memory to gmem */
+ if (zsbuf_cpp[0]) {
+ gmem->zsbuf_base[0] = align(total, gmem_align);
+ total = gmem->zsbuf_base[0] + zsbuf_cpp[0] * bin_w * bin_h;
+ }
-static void
-emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t base,
- struct pipe_surface *psurf)
-{
- struct fd_resource *rsc = fd_resource(psurf->texture);
- uint32_t swiz;
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
- OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(fmt2swap(psurf->format)) |
- A2XX_RB_COLOR_INFO_BASE(base) |
- A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
-
- swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
- PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
-
- /* emit fb as a texture: */
- OUT_PKT3(ring, CP_SET_CONSTANT, 7);
- OUT_RING(ring, 0x00010000);
- OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
- A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
- A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
- A2XX_SQ_TEX_0_PITCH(rsc->pitch));
- OUT_RELOC(ring, rsc->bo, 0,
- fd_pipe2surface(psurf->format) | 0x800);
- OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
- A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
- OUT_RING(ring, 0x01000000 | // XXX
- swiz |
- A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
- A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, 0x00000200);
-
- OUT_PKT3(ring, CP_DRAW_INDX, 3);
- OUT_RING(ring, 0x00000000);
- OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
- INDEX_SIZE_IGN, IGNORE_VISIBILITY));
- OUT_RING(ring, 3); /* NumIndices */
-}
+ if (zsbuf_cpp[1]) {
+ gmem->zsbuf_base[1] = align(total, gmem_align);
+ total = gmem->zsbuf_base[1] + zsbuf_cpp[1] * bin_w * bin_h;
+ }
-static void
-emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring,
- uint32_t xoff, uint32_t yoff, uint32_t bin_w, uint32_t bin_h)
-{
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
- float x0, y0, x1, y1;
-
- fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
- { .prsc = ctx->solid_vertexbuf, .size = 48, .offset = 0x30 },
- { .prsc = ctx->solid_vertexbuf, .size = 32, .offset = 0x60 },
- }, 2);
-
- /* write texture coordinates to vertexbuf: */
- x0 = ((float)xoff) / ((float)pfb->width);
- x1 = ((float)xoff + bin_w) / ((float)pfb->width);
- y0 = ((float)yoff) / ((float)pfb->height);
- y1 = ((float)yoff + bin_h) / ((float)pfb->height);
- OUT_PKT3(ring, CP_MEM_WRITE, 9);
- OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0);
- OUT_RING(ring, fui(x0));
- OUT_RING(ring, fui(y0));
- OUT_RING(ring, fui(x1));
- OUT_RING(ring, fui(y0));
- OUT_RING(ring, fui(x0));
- OUT_RING(ring, fui(y1));
- OUT_RING(ring, fui(x1));
- OUT_RING(ring, fui(y1));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
- OUT_RING(ring, 0);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
- OUT_RING(ring, 0x0000003b);
-
- fd_program_emit(ring, &ctx->blit_prog);
-
- OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
- OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
- OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
- OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
- A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
- A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
- OUT_RING(ring, 0x0000ffff);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
- OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
- A2XX_RB_COLORCONTROL_BLEND_DISABLE |
- A2XX_RB_COLORCONTROL_ROP_CODE(12) |
- A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
- A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
- OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
- A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
- A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
- A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
- A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
- A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 3);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
- OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
- xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
- OUT_RING(ring, xy2d(bin_w, bin_h)); /* PA_SC_WINDOW_SCISSOR_BR */
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 5);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
- OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */
- OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */
- OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
- OUT_RING(ring, fui((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
- OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
- A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this???
- A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
- A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
-
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
- OUT_RING(ring, 0x00000000);
-
- if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
- emit_mem2gmem_surf(ring, bin_w * bin_h, pfb->zsbuf);
-
- if (ctx->restore & FD_BUFFER_COLOR)
- emit_mem2gmem_surf(ring, 0, pfb->cbufs[0]);
-
- /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
+ return total;
}
static void
-calculate_tiles(struct fd_context *ctx)
+calculate_tiles(struct fd_batch *batch)
{
+ struct fd_context *ctx = batch->ctx;
+ struct fd_screen *screen = ctx->screen;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct pipe_scissor_state *scissor = &ctx->max_scissor;
- uint32_t cpp = util_format_get_blocksize(ctx->framebuffer.cbufs[0]->format);
- uint32_t gmem_size = ctx->screen->gmemsize_bytes;
+ struct pipe_scissor_state *scissor = &batch->max_scissor;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ const uint32_t gmem_alignw = screen->gmem_alignw;
+ const uint32_t gmem_alignh = screen->gmem_alignh;
+ const unsigned npipes = screen->num_vsc_pipes;
+ const uint32_t gmem_size = screen->gmemsize_bytes;
uint32_t minx, miny, width, height;
uint32_t nbins_x = 1, nbins_y = 1;
uint32_t bin_w, bin_h;
- uint32_t max_width = 992;
+ uint32_t gmem_align = 0x4000;
+ uint32_t max_width = bin_width(screen);
+ uint8_t cbuf_cpp[MAX_RENDER_TARGETS] = {0}, zsbuf_cpp[2] = {0};
+ uint32_t i, j, t, xoff, yoff;
+ uint32_t tpp_x, tpp_y;
+ bool has_zs = !!((batch->resolve | batch->restore) &
+ (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
+ int tile_n[npipes];
+
+ if (has_zs) {
+ struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
+ zsbuf_cpp[0] = rsc->cpp;
+ if (rsc->stencil)
+ zsbuf_cpp[1] = rsc->stencil->cpp;
+ }
+ for (i = 0; i < pfb->nr_cbufs; i++) {
+ if (pfb->cbufs[i])
+ cbuf_cpp[i] = util_format_get_blocksize(pfb->cbufs[i]->format);
+ else
+ cbuf_cpp[i] = 4;
+ /* if MSAA, color buffers are super-sampled in GMEM: */
+ cbuf_cpp[i] *= pfb->samples;
+ }
- if ((gmem->cpp == cpp) &&
- !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
+ if (!memcmp(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp)) &&
+ !memcmp(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp)) &&
+ !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
/* everything is up-to-date */
return;
}
- minx = scissor->minx & ~31; /* round down to multiple of 32 */
- miny = scissor->miny & ~31;
- width = scissor->maxx - minx;
- height = scissor->maxy - miny;
-
-// TODO we probably could optimize this a bit if we know that
-// Z or stencil is not enabled for any of the draw calls..
-// if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
- gmem_size /= 2;
- max_width = 256;
-// }
+ if (fd_mesa_debug & FD_DBG_NOSCIS) {
+ minx = 0;
+ miny = 0;
+ width = pfb->width;
+ height = pfb->height;
+ } else {
+ /* round down to multiple of alignment: */
+ minx = scissor->minx & ~(gmem_alignw - 1);
+ miny = scissor->miny & ~(gmem_alignh - 1);
+ width = scissor->maxx - minx;
+ height = scissor->maxy - miny;
+ }
- bin_w = align(width, 32);
- bin_h = align(height, 32);
+ bin_w = align(width, gmem_alignw);
+ bin_h = align(height, gmem_alignh);
/* first, find a bin width that satisfies the maximum width
* restrictions:
*/
while (bin_w > max_width) {
nbins_x++;
- bin_w = align(width / nbins_x, 32);
+ bin_w = align(width / nbins_x, gmem_alignw);
+ }
+
+ if (fd_mesa_debug & FD_DBG_MSGS) {
+ debug_printf("binning input: cbuf cpp:");
+ for (i = 0; i < pfb->nr_cbufs; i++)
+ debug_printf(" %d", cbuf_cpp[i]);
+ debug_printf(", zsbuf cpp: %d; %dx%d\n",
+ zsbuf_cpp[0], width, height);
+ }
+
+ if (is_a20x(screen) && batch->cleared) {
+ /* under normal circumstances the requirement would be 4K
+ * but the fast clear path requires an alignment of 32K
+ */
+ gmem_align = 0x8000;
}
- /* then find a bin height that satisfies the memory constraints:
+ /* then find a bin width/height that satisfies the memory
+ * constraints:
*/
- while ((bin_w * bin_h * cpp) > gmem_size) {
- nbins_y++;
- bin_h = align(height / nbins_y, 32);
+ while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem_align, gmem) >
+ gmem_size) {
+ if (bin_w > bin_h) {
+ nbins_x++;
+ bin_w = align(width / nbins_x, gmem_alignw);
+ } else {
+ nbins_y++;
+ bin_h = align(height / nbins_y, gmem_alignh);
+ }
}
DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
gmem->scissor = *scissor;
- gmem->cpp = cpp;
- gmem->minx = minx;
- gmem->miny = miny;
+ memcpy(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp));
+ memcpy(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp));
gmem->bin_h = bin_h;
gmem->bin_w = bin_w;
gmem->nbins_x = nbins_x;
gmem->nbins_y = nbins_y;
+ gmem->minx = minx;
+ gmem->miny = miny;
gmem->width = width;
gmem->height = height;
-}
-void
-fd_gmem_render_tiles(struct pipe_context *pctx)
-{
- struct fd_context *ctx = fd_context(pctx);
- struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
- struct fd_ringbuffer *ring = ctx->ring;
- enum a2xx_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format);
- uint32_t i, timestamp, yoff = 0;
- uint32_t reg;
+ /*
+ * Assign tiles and pipes:
+ *
+ * At some point it might be worth playing with different
+ * strategies and seeing if that makes much impact on
+ * performance.
+ */
+
+#define div_round_up(v, a) (((v) + (a) - 1) / (a))
+ /* figure out number of tiles per pipe: */
+ if (is_a20x(ctx->screen)) {
+ /* for a20x we want to minimize the number of "pipes"
+ * binning data has 3 bits for x/y (8x8) but the edges are used to
+ * cull off-screen vertices with hw binning, so we have 6x6 pipes
+ */
+ tpp_x = 6;
+ tpp_y = 6;
+ } else {
+ tpp_x = tpp_y = 1;
+ while (div_round_up(nbins_y, tpp_y) > screen->num_vsc_pipes)
+ tpp_y += 2;
+ while ((div_round_up(nbins_y, tpp_y) *
+ div_round_up(nbins_x, tpp_x)) > screen->num_vsc_pipes)
+ tpp_x += 1;
+ }
- calculate_tiles(ctx);
+ gmem->maxpw = tpp_x;
+ gmem->maxph = tpp_y;
- DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
- util_format_name(pfb->cbufs[0]->format),
- pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
+ /* configure pipes: */
+ xoff = yoff = 0;
+ for (i = 0; i < npipes; i++) {
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
- /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
- fd_ringmarker_mark(ctx->draw_end);
+ if (xoff >= nbins_x) {
+ xoff = 0;
+ yoff += tpp_y;
+ }
- /* RB_SURFACE_INFO / RB_DEPTH_INFO can be emitted once per tile pass,
- * but RB_COLOR_INFO gets overwritten by gmem2mem and mem2gmem and so
- * needs to be emitted for each tile:
- */
- OUT_PKT3(ring, CP_SET_CONSTANT, 4);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
- OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
- OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
- A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
- reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(align(gmem->bin_w * gmem->bin_h, 4));
- if (pfb->zsbuf)
- reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
- OUT_RING(ring, reg); /* RB_DEPTH_INFO */
-
- yoff= gmem->miny;
- for (i = 0; i < gmem->nbins_y; i++) {
- uint32_t j, xoff = gmem->minx;
- uint32_t bh = gmem->bin_h;
+ if (yoff >= nbins_y) {
+ break;
+ }
- /* clip bin height: */
- bh = MIN2(bh, gmem->height - yoff);
+ pipe->x = xoff;
+ pipe->y = yoff;
+ pipe->w = MIN2(tpp_x, nbins_x - xoff);
+ pipe->h = MIN2(tpp_y, nbins_y - yoff);
+
+ xoff += tpp_x;
+ }
- for (j = 0; j < gmem->nbins_x; j++) {
- uint32_t bw = gmem->bin_w;
+ /* number of pipes to use for a20x */
+ gmem->num_vsc_pipes = MAX2(1, i);
- /* clip bin width: */
- bw = MIN2(bw, gmem->width - xoff);
+ for (; i < npipes; i++) {
+ struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
+ pipe->x = pipe->y = pipe->w = pipe->h = 0;
+ }
- DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
- bh, yoff, bw, xoff);
+#if 0 /* debug */
+ printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
+ for (i = 0; i < 8; i++) {
+ struct fd_vsc_pipe *pipe = &ctx->pipe[i];
+ printf("pipe[%d]: %ux%u @ %u,%u\n", i,
+ pipe->w, pipe->h, pipe->x, pipe->y);
+ }
+#endif
+
+ /* configure tiles: */
+ t = 0;
+ yoff = miny;
+ memset(tile_n, 0, sizeof(tile_n));
+ for (i = 0; i < nbins_y; i++) {
+ uint32_t bw, bh;
- /* setup screen scissor for current tile (same for mem2gmem): */
- OUT_PKT3(ring, CP_SET_CONSTANT, 3);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
- OUT_RING(ring, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */
- OUT_RING(ring, xy2d(bw, bh)); /* PA_SC_SCREEN_SCISSOR_BR */
+ xoff = minx;
- if (ctx->restore)
- emit_mem2gmem(ctx, ring, xoff, yoff, bw, bh);
+ /* clip bin height: */
+ bh = MIN2(bin_h, miny + height - yoff);
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
- OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
- A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
+ for (j = 0; j < nbins_x; j++) {
+ struct fd_tile *tile = &ctx->tile[t];
+ uint32_t p;
- /* setup window scissor and offset for current tile (different
- * from mem2gmem):
- */
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
- OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff) |
- A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
+ assert(t < ARRAY_SIZE(ctx->tile));
- /* emit IB to drawcmds: */
- OUT_IB (ring, ctx->draw_start, ctx->draw_end);
+ /* pipe number: */
+ p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
+ assert(p < gmem->num_vsc_pipes);
- OUT_PKT3(ring, CP_SET_CONSTANT, 2);
- OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
- OUT_RING(ring, 0x00000000); /* PA_SC_WINDOW_OFFSET */
+ /* clip bin width: */
+ bw = MIN2(bin_w, minx + width - xoff);
+ tile->n = !is_a20x(ctx->screen) ? tile_n[p]++ :
+ ((i % tpp_y + 1) << 3 | (j % tpp_x + 1));
+ tile->p = p;
+ tile->bin_w = bw;
+ tile->bin_h = bh;
+ tile->xoff = xoff;
+ tile->yoff = yoff;
- /* emit gmem2mem to transfer tile back to system memory: */
- emit_gmem2mem(ctx, ring, xoff, yoff, bw, bh);
+ t++;
xoff += bw;
}
yoff += bh;
}
- /* GPU executes starting from tile cmds, which IB back to draw cmds: */
- fd_ringmarker_flush(ctx->draw_end);
+#if 0 /* debug */
+ t = 0;
+ for (i = 0; i < nbins_y; i++) {
+ for (j = 0; j < nbins_x; j++) {
+ struct fd_tile *tile = &ctx->tile[t++];
+ printf("|p:%u n:%u|", tile->p, tile->n);
+ }
+ printf("\n");
+ }
+#endif
+}
- /* mark start for next draw cmds: */
- fd_ringmarker_mark(ctx->draw_start);
+static void
+render_tiles(struct fd_batch *batch)
+{
+ struct fd_context *ctx = batch->ctx;
+ struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ int i;
- /* update timestamps on render targets: */
- fd_pipe_timestamp(ctx->screen->pipe, ×tamp);
- fd_resource(pfb->cbufs[0]->texture)->timestamp = timestamp;
- if (pfb->zsbuf)
- fd_resource(pfb->zsbuf->texture)->timestamp = timestamp;
+ ctx->emit_tile_init(batch);
- /* reset maximal bounds: */
- ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
- ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
+ if (batch->restore)
+ ctx->stats.batch_restore++;
- /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
- * after the draw/clear calls, but executed before, we need to preemptively
- * flag some state as dirty before the first draw/clear call.
- *
- * TODO maybe we need to mark all state as dirty to not worry about state
- * being clobbered by other contexts?
- */
- ctx->dirty |= FD_DIRTY_ZSA |
- FD_DIRTY_RASTERIZER |
- FD_DIRTY_FRAMEBUFFER |
- FD_DIRTY_SAMPLE_MASK |
- FD_DIRTY_VIEWPORT |
- FD_DIRTY_CONSTBUF |
- FD_DIRTY_PROG |
- FD_DIRTY_SCISSOR |
- /* probably only needed if we need to mem2gmem on the next
- * draw.. but not sure if there is a good way to know?
- */
- FD_DIRTY_VERTTEX |
- FD_DIRTY_FRAGTEX |
- FD_DIRTY_BLEND;
+ for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
+ struct fd_tile *tile = &ctx->tile[i];
+
+ DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
+ tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
+
+ ctx->emit_tile_prep(batch, tile);
+
+ if (batch->restore) {
+ ctx->emit_tile_mem2gmem(batch, tile);
+ }
+
+ ctx->emit_tile_renderprep(batch, tile);
+
+ if (ctx->query_prepare_tile)
+ ctx->query_prepare_tile(batch, i, batch->gmem);
+
+ /* emit IB to drawcmds: */
+ ctx->emit_ib(batch->gmem, batch->draw);
+ fd_reset_wfi(batch);
+
+ /* emit gmem2mem to transfer tile back to system memory: */
+ ctx->emit_tile_gmem2mem(batch, tile);
+ }
+
+ if (ctx->emit_tile_fini)
+ ctx->emit_tile_fini(batch);
+}
+
+static void
+render_sysmem(struct fd_batch *batch)
+{
+ struct fd_context *ctx = batch->ctx;
+
+ ctx->emit_sysmem_prep(batch);
+
+ if (ctx->query_prepare_tile)
+ ctx->query_prepare_tile(batch, 0, batch->gmem);
+
+ /* emit IB to drawcmds: */
+ ctx->emit_ib(batch->gmem, batch->draw);
+ fd_reset_wfi(batch);
+
+ if (ctx->emit_sysmem_fini)
+ ctx->emit_sysmem_fini(batch);
+}
+
+static void
+flush_ring(struct fd_batch *batch)
+{
+ uint32_t timestamp;
+ int out_fence_fd = -1;
+
+ fd_submit_flush(batch->submit, batch->in_fence_fd,
+ batch->needs_out_fence_fd ? &out_fence_fd : NULL,
+ ×tamp);
+
+ fd_fence_populate(batch->fence, timestamp, out_fence_fd);
+}
+
+void
+fd_gmem_render_tiles(struct fd_batch *batch)
+{
+ struct fd_context *ctx = batch->ctx;
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ bool sysmem = false;
+
+ if (ctx->emit_sysmem_prep && !batch->nondraw) {
+ if (batch->cleared || batch->gmem_reason ||
+ ((batch->num_draws > 5) && !batch->blit) ||
+ (pfb->samples > 1)) {
+ DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u, samples=%u",
+ batch->cleared, batch->gmem_reason, batch->num_draws,
+ pfb->samples);
+ } else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
+ sysmem = true;
+ }
+
+ /* For ARB_framebuffer_no_attachments: */
+ if ((pfb->nr_cbufs == 0) && !pfb->zsbuf) {
+ sysmem = true;
+ }
+ }
+
+ fd_reset_wfi(batch);
+
+ ctx->stats.batch_total++;
+
+ if (batch->nondraw) {
+ DBG("%p: rendering non-draw", batch);
+ ctx->stats.batch_nondraw++;
+ } else if (sysmem) {
+ DBG("%p: rendering sysmem %ux%u (%s/%s)",
+ batch, pfb->width, pfb->height,
+ util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
+ util_format_short_name(pipe_surface_format(pfb->zsbuf)));
+ if (ctx->query_prepare)
+ ctx->query_prepare(batch, 1);
+ render_sysmem(batch);
+ ctx->stats.batch_sysmem++;
+ } else {
+ struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ calculate_tiles(batch);
+ DBG("%p: rendering %dx%d tiles %ux%u (%s/%s)",
+ batch, pfb->width, pfb->height, gmem->nbins_x, gmem->nbins_y,
+ util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
+ util_format_short_name(pipe_surface_format(pfb->zsbuf)));
+ if (ctx->query_prepare)
+ ctx->query_prepare(batch, gmem->nbins_x * gmem->nbins_y);
+ render_tiles(batch);
+ ctx->stats.batch_gmem++;
+ }
+
+ flush_ring(batch);
+}
+
+/* When deciding whether a tile needs mem2gmem, we need to take into
+ * account the scissor rect(s) that were cleared. To simplify we only
+ * consider the last scissor rect for each buffer, since the common
+ * case would be a single clear.
+ */
+bool
+fd_gmem_needs_restore(struct fd_batch *batch, struct fd_tile *tile,
+ uint32_t buffers)
+{
+ if (!(batch->restore & buffers))
+ return false;
+
+ return true;
}
projects / mesa.git / blobdiff