gallium: add PIPE_SHADER_CAP_SUPPORTED_IRS

[mesa.git] / src / gallium / drivers / freedreno / freedreno_program.c

diff --git a/src/gallium/drivers/freedreno/freedreno_program.c b/src/gallium/drivers/freedreno/freedreno_program.c
index 52a165b64af6d0f4b1a35a3d68f90e1ed3222e62..e6a647852a3b99e0714e7ee9959da9588a1d6310 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_program.c
+++ b/src/gallium/drivers/freedreno/freedreno_program.c
@@ -92,11 +92,15 @@ static void * assemble_tgsi(struct pipe_context *pctx,
 }
 
 static void *
-fd_prog_blit(struct pipe_context *pctx, int rts)
+fd_prog_blit(struct pipe_context *pctx, int rts, bool depth)
 {
        int i;
        struct ureg_src tc;
-       struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
+       struct ureg_program *ureg;
+
+       debug_assert(rts <= MAX_RENDER_TARGETS);
+
+       ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT);
        if (!ureg)
                return NULL;
 
@@ -105,6 +109,12 @@ fd_prog_blit(struct pipe_context *pctx, int rts)
        for (i = 0; i < rts; i++)
                ureg_TEX(ureg, ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, i),
                                 TGSI_TEXTURE_2D, tc, ureg_DECL_sampler(ureg, i));
+       if (depth)
+               ureg_TEX(ureg,
+                                ureg_writemask(
+                                                ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
+                                                TGSI_WRITEMASK_Z),
+                                TGSI_TEXTURE_2D, tc, ureg_DECL_sampler(ureg, rts));
 
        ureg_END(ureg);
 
@@ -128,11 +138,16 @@ void fd_prog_init(struct pipe_context *pctx)
        ctx->solid_prog.fp = assemble_tgsi(pctx, solid_fp, true);
        ctx->solid_prog.vp = assemble_tgsi(pctx, solid_vp, false);
        ctx->blit_prog[0].vp = assemble_tgsi(pctx, blit_vp, false);
-       ctx->blit_prog[0].fp = fd_prog_blit(pctx, 1);
+       ctx->blit_prog[0].fp = fd_prog_blit(pctx, 1, false);
        for (i = 1; i < ctx->screen->max_rts; i++) {
                ctx->blit_prog[i].vp = ctx->blit_prog[0].vp;
-               ctx->blit_prog[i].fp = fd_prog_blit(pctx, i + 1);
+               ctx->blit_prog[i].fp = fd_prog_blit(pctx, i + 1, false);
        }
+
+       ctx->blit_z.vp = ctx->blit_prog[0].vp;
+       ctx->blit_z.fp = fd_prog_blit(pctx, 0, true);
+       ctx->blit_zs.vp = ctx->blit_prog[0].vp;
+       ctx->blit_zs.fp = fd_prog_blit(pctx, 1, true);
 }
 
 void fd_prog_fini(struct pipe_context *pctx)
@@ -145,4 +160,6 @@ void fd_prog_fini(struct pipe_context *pctx)
        pctx->delete_vs_state(pctx, ctx->blit_prog[0].vp);
        for (i = 0; i < ctx->screen->max_rts; i++)
                pctx->delete_fs_state(pctx, ctx->blit_prog[i].fp);
+       pctx->delete_fs_state(pctx, ctx->blit_z.fp);
+       pctx->delete_fs_state(pctx, ctx->blit_zs.fp);
 }