freedreno/ir3: change opt passes

[mesa.git] / src / gallium / drivers / freedreno / freedreno_resource.h

diff --git a/src/gallium/drivers/freedreno/freedreno_resource.h b/src/gallium/drivers/freedreno/freedreno_resource.h
index 9833b30e17fdb48f006256011f434dc5e36bb60b..2834969110bfad06dbcbd18a44587698609f336e 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_resource.h
+++ b/src/gallium/drivers/freedreno/freedreno_resource.h
@@ -31,8 +31,9 @@
 
 #include "util/list.h"
 #include "util/u_range.h"
-#include "util/u_transfer.h"
+#include "util/u_transfer_helper.h"
 
+#include "freedreno_batch.h"
 #include "freedreno_util.h"
 
 /* Texture Layout on a3xx:
@@ -60,22 +61,53 @@ struct fd_resource_slice {
        uint32_t size0;          /* size of first layer in slice */
 };
 
+struct set;
+
 struct fd_resource {
-       struct u_resource base;
+       struct pipe_resource base;
        struct fd_bo *bo;
        uint32_t cpp;
+       enum pipe_format internal_format;
        bool layer_first;        /* see above description */
        uint32_t layer_size;
        struct fd_resource_slice slices[MAX_MIP_LEVELS];
-       uint32_t timestamp;
-       bool dirty, reading;
        /* buffer range that has been initialized */
        struct util_range valid_buffer_range;
+       bool valid;
 
        /* reference to the resource holding stencil data for a z32_s8 texture */
+       /* TODO rename to secondary or auxiliary? */
        struct fd_resource *stencil;
 
-       struct list_head list;
+       /* bitmask of in-flight batches which reference this resource.  Note
+        * that the batch doesn't hold reference to resources (but instead
+        * the fd_ringbuffer holds refs to the underlying fd_bo), but in case
+        * the resource is destroyed we need to clean up the batch's weak
+        * references to us.
+        */
+       uint32_t batch_mask;
+
+       /* reference to batch that writes this resource: */
+       struct fd_batch *write_batch;
+
+       /* Set of batches whose batch-cache key references this resource.
+        * We need to track this to know which batch-cache entries to
+        * invalidate if, for example, the resource is invalidated or
+        * shadowed.
+        */
+       uint32_t bc_batch_mask;
+
+       unsigned tile_mode : 2;
+       unsigned preferred_tile_mode : 2;
+
+       /*
+        * LRZ
+        */
+       bool lrz_valid : 1;
+       uint16_t lrz_width;  // for lrz clear, does this differ from lrz_pitch?
+       uint16_t lrz_height;
+       uint16_t lrz_pitch;
+       struct fd_bo *lrz;
 };
 
 static inline struct fd_resource *
@@ -84,9 +116,27 @@ fd_resource(struct pipe_resource *ptex)
        return (struct fd_resource *)ptex;
 }
 
+static inline bool
+pending(struct fd_resource *rsc, bool write)
+{
+       /* if we have a pending GPU write, we are busy in any case: */
+       if (rsc->write_batch)
+               return true;
+
+       /* if CPU wants to write, but we are pending a GPU read, we are busy: */
+       if (write && rsc->batch_mask)
+               return true;
+
+       if (rsc->stencil && pending(rsc->stencil, write))
+               return true;
+
+       return false;
+}
+
 struct fd_transfer {
        struct pipe_transfer base;
-       void *staging;
+       struct pipe_resource *staging_prsc;
+       struct pipe_box staging_box;
 };
 
 static inline struct fd_transfer *
@@ -98,7 +148,7 @@ fd_transfer(struct pipe_transfer *ptrans)
 static inline struct fd_resource_slice *
 fd_resource_slice(struct fd_resource *rsc, unsigned level)
 {
-       assert(level <= rsc->base.b.last_level);
+       assert(level <= rsc->base.last_level);
        return &rsc->slices[level];
 }
 
@@ -117,7 +167,26 @@ fd_resource_offset(struct fd_resource *rsc, unsigned level, unsigned layer)
        return offset;
 }
 
+/* This might be a5xx specific, but higher mipmap levels are always linear: */
+static inline bool
+fd_resource_level_linear(struct pipe_resource *prsc, int level)
+{
+       unsigned w = u_minify(prsc->width0, level);
+       if (w < 16)
+               return true;
+       return false;
+}
+
+void fd_blitter_pipe_begin(struct fd_context *ctx, bool render_cond, bool discard,
+               enum fd_render_stage stage);
+void fd_blitter_pipe_end(struct fd_context *ctx);
+
 void fd_resource_screen_init(struct pipe_screen *pscreen);
 void fd_resource_context_init(struct pipe_context *pctx);
 
+uint32_t fd_setup_slices(struct fd_resource *rsc);
+void fd_resource_resize(struct pipe_resource *prsc, uint32_t sz);
+
+bool fd_render_condition_check(struct pipe_context *pctx);
+
 #endif /* FREEDRENO_RESOURCE_H_ */