#include "a2xx/fd2_screen.h"
#include "a3xx/fd3_screen.h"
#include "a4xx/fd4_screen.h"
+#include "a5xx/fd5_screen.h"
#include "ir3/ir3_nir.h"
{"flush", FD_DBG_FLUSH, "Force flush after every draw"},
{"deqp", FD_DBG_DEQP, "Enable dEQP hacks"},
{"nir", FD_DBG_NIR, "Prefer NIR as native IR"},
+ {"reorder", FD_DBG_REORDER,"Enable reordering for draws/blits"},
+ {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"},
DEBUG_NAMED_VALUE_END
};
if (screen->dev)
fd_device_del(screen->dev);
+ fd_bc_fini(&screen->batch_cache);
+
+ slab_destroy_parent(&screen->transfer_pool);
+
+ pipe_mutex_destroy(screen->lock);
+
free(screen);
}
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_STRING_MARKER:
+ case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
case PIPE_CAP_USER_CONSTANT_BUFFERS:
- return is_ir3(screen) ? 0 : 1;
+ return is_a4xx(screen) ? 0 : 1;
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_CLIP_HALFZ:
- return is_a3xx(screen) || is_a4xx(screen);
+ return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
return 0;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
if (is_a3xx(screen)) return 16;
if (is_a4xx(screen)) return 32;
+ if (is_a5xx(screen)) return 32;
return 0;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
/* We could possibly emulate more by pretending 2d/rect textures and
*/
if (is_a3xx(screen)) return 8192;
if (is_a4xx(screen)) return 16384;
+ if (is_a5xx(screen)) return 16384;
return 0;
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_TEXTURE_QUERY_LOD:
- return is_a4xx(screen);
+ return is_a4xx(screen) || is_a5xx(screen);
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 64;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (glsl120)
return 120;
+ // XXX temporary, avoid issues with glamor:
+ if (is_a5xx(screen))
+ return 120;
return is_ir3(screen) ? 140 : 120;
/* Unsupported features. */
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
+ case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+ case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
+ case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
return 0;
case PIPE_CAP_MAX_VIEWPORTS:
return PIPE_MAX_SO_BUFFERS;
return 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
if (is_ir3(screen))
return 1;
return 0;
return 11;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0;
+ return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0;
/* Render targets. */
case PIPE_CAP_MAX_RENDER_TARGETS:
return is_a3xx(screen) ? 1 : 0;
/* Queries. */
- case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
return 0;
case PIPE_CAP_OCCLUSION_QUERY:
- return is_a3xx(screen) || is_a4xx(screen);
+ return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
+ case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_TIME_ELAPSED:
/* only a4xx, requires new enough kernel so we know max_freq: */
return (screen->max_freq > 0) && is_a4xx(screen);
return 10;
case PIPE_CAP_UMA:
return 1;
+ case PIPE_CAP_NATIVE_FENCE_FD:
+ return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
}
debug_printf("unknown param %d\n", param);
return 0;
* split between VS and FS. Use lower limit of 256 to
* avoid getting into impossible situations:
*/
- return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]);
+ return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return is_ir3(screen) ? 16 : 1;
case PIPE_SHADER_CAP_MAX_PREDS:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
return 0;
}
debug_printf("unknown shader param %d\n", param);
struct fd_bo *
fd_screen_bo_from_handle(struct pipe_screen *pscreen,
- struct winsys_handle *whandle,
- unsigned *out_stride)
+ struct winsys_handle *whandle)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd_bo *bo;
return NULL;
}
- *out_stride = whandle->stride;
-
return bo;
}
case 430:
fd4_screen_init(pscreen);
break;
+ case 530:
+ fd5_screen_init(pscreen);
+ break;
default:
debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
goto fail;
}
+ if (screen->gpu_id >= 500) {
+ screen->gmem_alignw = 64;
+ screen->gmem_alignh = 32;
+ } else {
+ screen->gmem_alignw = 32;
+ screen->gmem_alignh = 32;
+ }
+
+ /* NOTE: don't enable reordering on a2xx, since completely untested.
+ * Also, don't enable if we have too old of a kernel to support
+ * growable cmdstream buffers, since memory requirement for cmdstream
+ * buffers would be too much otherwise.
+ */
+ if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
+ screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
+
+ fd_bc_init(&screen->batch_cache);
+
+ pipe_mutex_init(screen->lock);
+
pscreen->destroy = fd_screen_destroy;
pscreen->get_param = fd_screen_get_param;
pscreen->get_paramf = fd_screen_get_paramf;
pscreen->get_timestamp = fd_screen_get_timestamp;
- pscreen->fence_reference = fd_screen_fence_ref;
- pscreen->fence_finish = fd_screen_fence_finish;
+ pscreen->fence_reference = fd_fence_ref;
+ pscreen->fence_finish = fd_fence_finish;
+ pscreen->fence_get_fd = fd_fence_get_fd;
+
+ slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
util_format_s3tc_init();
projects / mesa.git / blobdiff