freedreno/a4xx: add fake RGTC support (required for GL3)
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
index b64f78ca32b699045dedc6ad7156b5ba0f20eb3b..456917730d60914bd870f4275a62065599c2150a 100644 (file)
@@ -160,7 +160,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_SHADER_STENCIL_EXPORT:
        case PIPE_CAP_TGSI_TEXCOORD:
        case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
-       case PIPE_CAP_CONDITIONAL_RENDER:
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
        case PIPE_CAP_TEXTURE_BARRIER:
        case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -176,19 +175,21 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_INDEP_BLEND_FUNC:
        case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
        case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
+       case PIPE_CAP_CONDITIONAL_RENDER:
+       case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
+       case PIPE_CAP_FAKE_SW_MSAA:
                return is_a3xx(screen) || is_a4xx(screen);
 
        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
-               /* ignoring first/last_element.. but I guess that should be
-                * easy to add..
-                */
-               return 0;
+               return is_a3xx(screen) ? 16 : 0;
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
                /* I think 32k on a4xx.. and we could possibly emulate more
                 * by pretending 2d/rect textures and splitting high bits
                 * of index into 2nd dimension..
                 */
-               return 16383;
+               if (is_a3xx(screen)) return 8192;
+               if (is_a4xx(screen)) return 16383;
+               return 0;
 
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
        case PIPE_CAP_CLIP_HALFZ:
@@ -205,7 +206,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
                if (glsl120)
                        return 120;
-               return is_ir3(screen) ? 130 : 120;
+               return is_ir3(screen) ? 140 : 120;
 
        /* Unsupported features. */
        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -220,14 +221,12 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
        case PIPE_CAP_TEXTURE_GATHER_SM5:
-       case PIPE_CAP_FAKE_SW_MSAA:
        case PIPE_CAP_TEXTURE_QUERY_LOD:
        case PIPE_CAP_SAMPLE_SHADING:
        case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
        case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
        case PIPE_CAP_DRAW_INDIRECT:
        case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
-       case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
        case PIPE_CAP_SAMPLER_VIEW_TARGET:
        case PIPE_CAP_POLYGON_OFFSET_CLAMP:
        case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
@@ -237,6 +236,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_DEPTH_BOUNDS_TEST:
        case PIPE_CAP_TGSI_TXQS:
        case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+       case PIPE_CAP_SHAREABLE_SHADERS:
+       case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
+       case PIPE_CAP_CLEAR_TEXTURE:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
@@ -411,6 +413,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
                return 16;
        case PIPE_SHADER_CAP_PREFERRED_IR:
                return PIPE_SHADER_IR_TGSI;
+       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
+               return 32;
        }
        debug_printf("unknown shader param %d\n", param);
        return 0;
@@ -545,6 +549,7 @@ fd_screen_create(struct fd_device *dev)
        case 220:
                fd2_screen_init(pscreen);
                break;
+       case 305:
        case 307:
        case 320:
        case 330: