gallium: switch boolean -> bool at the interface definitions
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
index 33f14b8f24828867336f505f120ede0aa30111ad..4fbe6dd92238d00b61b6691c5ffed5bd74924467 100644 (file)
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
 /*
  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
  *
@@ -41,6 +39,7 @@
 
 #include "util/os_time.h"
 
+#include "drm-uapi/drm_fourcc.h"
 #include <errno.h>
 #include <stdio.h>
 #include <stdlib.h>
 
 
 #include "ir3/ir3_nir.h"
+#include "a2xx/ir2.h"
 
 /* XXX this should go away */
 #include "state_tracker/drm_driver.h"
 
 static const struct debug_named_value debug_options[] = {
                {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
-               {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
+               {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
                {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
                {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
                {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
@@ -74,7 +74,6 @@ static const struct debug_named_value debug_options[] = {
                {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
                {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
                {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
-               {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
                {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
                {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
                {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
@@ -88,6 +87,7 @@ static const struct debug_named_value debug_options[] = {
                {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
                {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
                {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
+               {"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
                DEBUG_NAMED_VALUE_END
 };
 
@@ -97,22 +97,11 @@ int fd_mesa_debug = 0;
 bool fd_binning_enabled = true;
 static bool glsl120 = false;
 
-static const struct debug_named_value shader_debug_options[] = {
-               {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
-               {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
-               {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
-               DEBUG_NAMED_VALUE_END
-};
-
-DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
-
-enum fd_shader_debug fd_shader_debug = 0;
-
 static const char *
 fd_screen_get_name(struct pipe_screen *pscreen)
 {
        static char buffer[128];
-       util_snprintf(buffer, sizeof(buffer), "FD%03d",
+       snprintf(buffer, sizeof(buffer), "FD%03d",
                        fd_screen(pscreen)->device_id);
        return buffer;
 }
@@ -158,6 +147,9 @@ fd_screen_destroy(struct pipe_screen *pscreen)
        if (screen->dev)
                fd_device_del(screen->dev);
 
+       if (screen->ro)
+               FREE(screen->ro);
+
        fd_bc_fini(&screen->batch_cache);
 
        slab_destroy_parent(&screen->transfer_pool);
@@ -204,6 +196,13 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_INVALIDATE_BUFFER:
                return 1;
 
+       case PIPE_CAP_PACKED_UNIFORMS:
+               return !is_a2xx(screen);
+
+       case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+       case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
+               return screen->has_robustness;
+
        case PIPE_CAP_VERTEXID_NOBASE:
                return is_a3xx(screen) || is_a4xx(screen);
 
@@ -218,7 +217,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
                return 0;
 
-       case PIPE_CAP_SM3:
+       case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+       case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+       case PIPE_CAP_VERTEX_SHADER_SATURATE:
        case PIPE_CAP_PRIMITIVE_RESTART:
        case PIPE_CAP_TGSI_INSTANCEID:
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
@@ -238,6 +239,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
                return is_a5xx(screen) || is_a6xx(screen);
 
+       case PIPE_CAP_SURFACE_SAMPLE_COUNT:
+               return is_a6xx(screen);
+
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
                return is_a3xx(screen) || is_a4xx(screen);
 
@@ -248,7 +252,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                if (is_a3xx(screen)) return 16;
                if (is_a4xx(screen)) return 32;
                if (is_a5xx(screen)) return 32;
-               if (is_a6xx(screen)) return 32;
+               if (is_a6xx(screen)) return 64;
                return 0;
        case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
                /* We could possibly emulate more by pretending 2d/rect textures and
@@ -257,7 +261,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                if (is_a3xx(screen)) return 8192;
                if (is_a4xx(screen)) return 16384;
                if (is_a5xx(screen)) return 16384;
-               if (is_a6xx(screen)) return 16384;
+               if (is_a6xx(screen)) return 1 << 27;
                return 0;
 
        case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
@@ -283,9 +287,16 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                        return 120;
                return is_ir3(screen) ? 140 : 120;
 
+       case PIPE_CAP_ESSL_FEATURE_LEVEL:
+               /* we can probably enable 320 for a5xx too, but need to test: */
+               if (is_a6xx(screen)) return 320;
+               if (is_a5xx(screen)) return 310;
+               if (is_ir3(screen))  return 300;
+               return 120;
+
        case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
-               if (is_a5xx(screen) || is_a6xx(screen))
-                       return 4;
+               if (is_a6xx(screen)) return 64;
+               if (is_a5xx(screen)) return 4;
                return 0;
 
        case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
@@ -297,6 +308,15 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
                return 0;
 
+       case PIPE_CAP_FBFETCH:
+               if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
+                               is_a6xx(screen))
+                       return 1;
+               return 0;
+       case PIPE_CAP_SAMPLE_SHADING:
+               if (is_a6xx(screen)) return 1;
+               return 0;
+
        case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
                return 0;
 
@@ -322,6 +342,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_VIEWPORTS:
                return 1;
 
+       case PIPE_CAP_MAX_VARYINGS:
+               return 16;
+
        case PIPE_CAP_SHAREABLE_SHADERS:
        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
        /* manage the variants for these ourself, to avoid breaking precompile: */
@@ -338,6 +361,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return 0;
        case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
        case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
+       case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
                if (is_ir3(screen))
                        return 1;
                return 0;
@@ -348,7 +372,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return 0;
 
        /* Texturing. */
-       case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+       case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+               return 1 << (MAX_MIP_LEVELS - 1);
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
                return MAX_MIP_LEVELS;
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
@@ -506,16 +531,9 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
                return 16;
        case PIPE_SHADER_CAP_PREFERRED_IR:
-               if (is_ir3(screen))
-                       return PIPE_SHADER_IR_NIR;
-               return PIPE_SHADER_IR_TGSI;
+               return PIPE_SHADER_IR_NIR;
        case PIPE_SHADER_CAP_SUPPORTED_IRS:
-               if (is_ir3(screen)) {
-                       return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
-               } else {
-                       return (1 << PIPE_SHADER_IR_TGSI);
-               }
-               return 0;
+               return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
                return 32;
        case PIPE_SHADER_CAP_SCALAR_ISA:
@@ -590,7 +608,7 @@ fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 
        case PIPE_COMPUTE_CAP_IR_TARGET:
                if (ret)
-                       sprintf(ret, ir);
+                       sprintf(ret, "%s", ir);
                return strlen(ir) * sizeof(char);
 
        case PIPE_COMPUTE_CAP_GRID_DIMENSION:
@@ -646,12 +664,13 @@ fd_get_compiler_options(struct pipe_screen *pscreen,
        if (is_ir3(screen))
                return ir3_get_compiler_options(screen->compiler);
 
-       return NULL;
+       return ir2_get_compiler_options();
 }
 
-boolean
+bool
 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
                struct fd_bo *bo,
+               struct renderonly_scanout *scanout,
                unsigned stride,
                struct winsys_handle *whandle)
 {
@@ -660,14 +679,47 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen,
        if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
                return fd_bo_get_name(bo, &whandle->handle) == 0;
        } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
+               if (renderonly_get_handle(scanout, whandle))
+                       return true;
                whandle->handle = fd_bo_handle(bo);
-               return TRUE;
+               return true;
        } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
                whandle->handle = fd_bo_dmabuf(bo);
-               return TRUE;
+               return true;
        } else {
-               return FALSE;
+               return false;
+       }
+}
+
+static void
+fd_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
+               enum pipe_format format,
+               int max, uint64_t *modifiers,
+               unsigned int *external_only,
+               int *count)
+{
+       struct fd_screen *screen = fd_screen(pscreen);
+       int i, num = 0;
+
+       max = MIN2(max, screen->num_supported_modifiers);
+
+       if (!max) {
+               max = screen->num_supported_modifiers;
+               external_only = NULL;
+               modifiers = NULL;
        }
+
+       for (i = 0; i < max; i++) {
+               if (modifiers)
+                       modifiers[num] = screen->supported_modifiers[i];
+
+               if (external_only)
+                       external_only[num] = 0;
+
+               num++;
+       }
+
+       *count = num;
 }
 
 struct fd_bo *
@@ -697,14 +749,13 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 }
 
 struct pipe_screen *
-fd_screen_create(struct fd_device *dev)
+fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 {
        struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
        struct pipe_screen *pscreen;
        uint64_t val;
 
        fd_mesa_debug = debug_get_option_fd_mesa_debug();
-       fd_shader_debug = debug_get_option_fd_shader_debug();
 
        if (fd_mesa_debug & FD_DBG_NOBIN)
                fd_binning_enabled = false;
@@ -719,6 +770,14 @@ fd_screen_create(struct fd_device *dev)
        screen->dev = dev;
        screen->refcnt = 1;
 
+       if (ro) {
+               screen->ro = renderonly_dup(ro);
+               if (!screen->ro) {
+                       DBG("could not create renderonly object");
+                       goto fail;
+               }
+       }
+
        // maybe this should be in context?
        screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
        if (!screen->pipe) {
@@ -732,6 +791,10 @@ fd_screen_create(struct fd_device *dev)
        }
        screen->gmemsize_bytes = val;
 
+       if (fd_device_version(dev) >= FD_VERSION_GMEM_BASE) {
+               fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
+       }
+
        if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
                DBG("could not get device-id");
                goto fail;
@@ -776,6 +839,11 @@ fd_screen_create(struct fd_device *dev)
                screen->priority_mask = (1 << val) - 1;
        }
 
+       if ((fd_device_version(dev) >= FD_VERSION_ROBUSTNESS) &&
+                       (fd_pipe_get_param(screen->pipe, FD_PP_PGTABLE, &val) == 0)) {
+               screen->has_robustness = val;
+       }
+
        struct sysinfo si;
        sysinfo(&si);
        screen->ram_size = si.totalram;
@@ -797,6 +865,8 @@ fd_screen_create(struct fd_device *dev)
         * send a patch ;-)
         */
        switch (screen->gpu_id) {
+       case 200:
+       case 201:
        case 205:
        case 220:
                fd2_screen_init(pscreen);
@@ -812,6 +882,7 @@ fd_screen_create(struct fd_device *dev)
                fd4_screen_init(pscreen);
                break;
        case 530:
+       case 540:
                fd5_screen_init(pscreen);
                break;
        case 630:
@@ -822,7 +893,11 @@ fd_screen_create(struct fd_device *dev)
                goto fail;
        }
 
-       if (screen->gpu_id >= 500) {
+       if (screen->gpu_id >= 600) {
+               screen->gmem_alignw = 32;
+               screen->gmem_alignh = 32;
+               screen->num_vsc_pipes = 32;
+       } else if (screen->gpu_id >= 500) {
                screen->gmem_alignw = 64;
                screen->gmem_alignh = 32;
                screen->num_vsc_pipes = 16;
@@ -832,12 +907,11 @@ fd_screen_create(struct fd_device *dev)
                screen->num_vsc_pipes = 8;
        }
 
-       /* NOTE: don't enable reordering on a2xx, since completely untested.
-        * Also, don't enable if we have too old of a kernel to support
+       /* NOTE: don't enable if we have too old of a kernel to support
         * growable cmdstream buffers, since memory requirement for cmdstream
         * buffers would be too much otherwise.
         */
-       if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
+       if (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)
                screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 
        fd_bc_init(&screen->batch_cache);
@@ -864,6 +938,17 @@ fd_screen_create(struct fd_device *dev)
        pscreen->fence_finish = fd_fence_finish;
        pscreen->fence_get_fd = fd_fence_get_fd;
 
+       pscreen->query_dmabuf_modifiers = fd_screen_query_dmabuf_modifiers;
+
+       if (!screen->supported_modifiers) {
+               static const uint64_t supported_modifiers[] = {
+                       DRM_FORMAT_MOD_LINEAR,
+               };
+
+               screen->supported_modifiers = supported_modifiers;
+               screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
+       }
+
        slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 
        return pscreen;