gallium: add PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS

[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 0b488b1834b867ac1841c6005a5cbe27df259ad6..93b434b0bac564f58fe9caef0ee0bdebd4f1d6d8 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -76,7 +76,7 @@ static const struct debug_named_value debug_options[] = {
                {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
                {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
                {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
-               {"reorder",   FD_DBG_REORDER,"Enable reordering for draws/blits"},
+               {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
                {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
                {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
                DEBUG_NAMED_VALUE_END
@@ -144,6 +144,8 @@ fd_screen_destroy(struct pipe_screen *pscreen)
 
        mtx_destroy(&screen->lock);
 
+       ralloc_free(screen->compiler);
+
        free(screen);
 }
 
@@ -299,6 +301,12 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_DOUBLES:
        case PIPE_CAP_INT64:
        case PIPE_CAP_INT64_DIVMOD:
+       case PIPE_CAP_TGSI_TEX_TXF_LZ:
+       case PIPE_CAP_TGSI_CLOCK:
+       case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+       case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
+       case PIPE_CAP_TGSI_BALLOT:
+       case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
@@ -472,8 +480,6 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
                return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]);
        case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
                return is_ir3(screen) ? 16 : 1;
-       case PIPE_SHADER_CAP_MAX_PREDS:
-               return 0; /* nothing uses this */
        case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
                return 1;
        case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
@@ -514,6 +520,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
        case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
        case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
+       case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
                return 0;
        }
        debug_printf("unknown shader param %d\n", param);
@@ -702,7 +709,7 @@ fd_screen_create(struct fd_device *dev)
         * buffers would be too much otherwise.
         */
        if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
-               screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER);
+               screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 
        fd_bc_init(&screen->batch_cache);