#include <errno.h>
#include <stdlib.h>
-#include "freedreno_context.h"
#include "freedreno_screen.h"
#include "freedreno_resource.h"
#include "freedreno_fence.h"
+#include "freedreno_query.h"
#include "freedreno_util.h"
+#include "fd2_screen.h"
+#include "fd3_screen.h"
+
/* XXX this should go away */
#include "state_tracker/drm_driver.h"
{"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
{"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"},
{"dgmem", FD_DBG_DGMEM, "Mark all state dirty after GMEM tile pass"},
+ {"dscis", FD_DBG_DSCIS, "Disable scissor optimization"},
+ {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
+ {"dbypass", FD_DBG_DBYPASS,"Disable GMEM bypass"},
+ {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
+ {"nobin", FD_DBG_NOBIN, "Disable hw binning"},
+ {"noopt", FD_DBG_NOOPT , "Disable optimization passes in compiler"},
+ {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
+ {"optdump", FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
+ {"glsl130", FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"},
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
int fd_mesa_debug = 0;
+bool fd_binning_enabled = true;
+static bool glsl130 = false;
static const char *
fd_screen_get_name(struct pipe_screen *pscreen)
}
/*
-EGL Version 1.4
-EGL Vendor Qualcomm, Inc
-EGL Extensions EGL_QUALCOMM_shared_image EGL_KHR_image EGL_AMD_create_image EGL_KHR_lock_surface EGL_KHR_lock_surface2 EGL_KHR_fence_sync EGL_IMG_context_priorityEGL_ANDROID_image_native_buffer
-GL extensions: GL_AMD_compressed_ATC_texture GL_AMD_performance_monitor GL_AMD_program_binary_Z400 GL_EXT_texture_filter_anisotropic GL_EXT_texture_format_BGRA8888 GL_EXT_texture_type_2_10_10_10_REV GL_NV_fence GL_OES_compressed_ETC1_RGB8_texture GL_OES_depth_texture GL_OES_depth24 GL_OES_EGL_image GL_OES_EGL_image_external GL_OES_element_index_uint GL_OES_fbo_render_mipmap GL_OES_fragment_precision_high GL_OES_get_program_binary GL_OES_packed_depth_stencil GL_OES_rgb8_rgba8 GL_OES_standard_derivatives GL_OES_texture_3D GL_OES_texture_float GL_OES_texture_half_float GL_OES_texture_half_float_linear GL_OES_texture_npot GL_OES_vertex_half_float GL_OES_vertex_type_10_10_10_2 GL_QCOM_alpha_test GL_QCOM_binning_control GL_QCOM_driver_control GL_QCOM_perfmon_global_mode GL_QCOM_extended_get GL_QCOM_extended_get2 GL_QCOM_tiled_rendering GL_QCOM_writeonly_rendering GL_AMD_compressed_3DC_texture
-GL_MAX_3D_TEXTURE_SIZE_OES: 1024 0 0 0
-no GL_MAX_SAMPLES_ANGLE: GL_INVALID_ENUM
-no GL_MAX_SAMPLES_APPLE: GL_INVALID_ENUM
-GL_MAX_TEXTURE_MAX_ANISOTROPY_EXT: 16 0 0 0
-no GL_MAX_SAMPLES_IMG: GL_INVALID_ENUM
-GL_MAX_TEXTURE_SIZE: 4096 0 0 0
-GL_MAX_VIEWPORT_DIMS: 4096 4096 0 0
-GL_MAX_VERTEX_ATTRIBS: 16 0 0 0
-GL_MAX_VERTEX_UNIFORM_VECTORS: 251 0 0 0
-GL_MAX_VARYING_VECTORS: 8 0 0 0
-GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS: 20 0 0 0
-GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS: 4 0 0 0
-GL_MAX_TEXTURE_IMAGE_UNITS: 16 0 0 0
-GL_MAX_FRAGMENT_UNIFORM_VECTORS: 221 0 0 0
-GL_MAX_CUBE_MAP_TEXTURE_SIZE: 4096 0 0 0
-GL_MAX_RENDERBUFFER_SIZE: 4096 0 0 0
-no GL_TEXTURE_NUM_LEVELS_QCOM: GL_INVALID_ENUM
+TODO either move caps to a2xx/a3xx specific code, or maybe have some
+tables for things that differ if the delta is not too much..
*/
static int
fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
+ struct fd_screen *screen = fd_screen(pscreen);
+
/* this is probably not totally correct.. but it's a start: */
switch (param) {
/* Supported features (boolean caps). */
case PIPE_CAP_NPOT_TEXTURES:
+ case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_SWIZZLE:
- case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_SM3:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
- case PIPE_CAP_PRIMITIVE_RESTART:
- case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
return 1;
+ case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+ case PIPE_CAP_CONDITIONAL_RENDER:
+ case PIPE_CAP_PRIMITIVE_RESTART:
return 0;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- return 120;
+ return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120;
/* Unsupported features. */
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- case PIPE_CAP_SCALED_RESOLVE:
- case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
+ case PIPE_CAP_TGSI_VS_LAYER:
+ case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+ case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
+ case PIPE_CAP_FAKE_SW_MSAA:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
+ case PIPE_CAP_SAMPLE_SHADING:
+ case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
return 0;
/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 0;
+ /* Geometry shader output, unsupported. */
+ case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
+ case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
+ return 0;
+
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 14;
+ return MAX_MIP_LEVELS;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 9192;
- case PIPE_CAP_MAX_COMBINED_SAMPLERS:
- return 20;
/* Render targets. */
case PIPE_CAP_MAX_RENDER_TARGETS:
return 1;
- /* Timer queries. */
+ /* Queries. */
case PIPE_CAP_QUERY_TIME_ELAPSED:
- case PIPE_CAP_OCCLUSION_QUERY:
case PIPE_CAP_QUERY_TIMESTAMP:
return 0;
+ case PIPE_CAP_OCCLUSION_QUERY:
+ return (screen->gpu_id >= 300) ? 1 : 0;
+ case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MIN_TEXEL_OFFSET:
return -8;
+ case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
+ case PIPE_CAP_ENDIANNESS:
+ return PIPE_ENDIAN_LITTLE;
+
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return 64;
+
default:
DBG("unknown param %d", param);
return 0;
fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
enum pipe_shader_cap param)
{
+ struct fd_screen *screen = fd_screen(pscreen);
+
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 8; /* XXX */
case PIPE_SHADER_CAP_MAX_INPUTS:
- return 32;
+ return 16;
case PIPE_SHADER_CAP_MAX_TEMPS:
- return 256; /* Max native temporaries. */
+ return 64; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_ADDRS:
- /* XXX Isn't this equal to TEMPS? */
return 1; /* Max native address registers */
case PIPE_SHADER_CAP_MAX_CONSTS:
+ return (screen->gpu_id >= 300) ? 1024 : 64;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return 64;
+ return 1;
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
+ return 1;
case PIPE_SHADER_CAP_INTEGERS:
- return 0;
+ /* we should be able to support this on a3xx, but not
+ * implemented yet:
+ */
+ return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
+ case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
return 0;
}
-static boolean
-fd_screen_is_format_supported(struct pipe_screen *pscreen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned usage)
-{
- unsigned retval = 0;
-
- if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
- (sample_count > 1) || /* TODO add MSAA */
- !util_format_is_supported(format, usage)) {
- DBG("not supported: format=%s, target=%d, sample_count=%d, usage=%x",
- util_format_name(format), target, sample_count, usage);
- return FALSE;
- }
-
- /* TODO figure out how to render to other formats.. */
- if ((usage & PIPE_BIND_RENDER_TARGET) &&
- ((format != PIPE_FORMAT_B8G8R8A8_UNORM) &&
- (format != PIPE_FORMAT_B8G8R8X8_UNORM))) {
- DBG("not supported render target: format=%s, target=%d, sample_count=%d, usage=%x",
- util_format_name(format), target, sample_count, usage);
- return FALSE;
- }
-
- if ((usage & (PIPE_BIND_SAMPLER_VIEW |
- PIPE_BIND_VERTEX_BUFFER)) &&
- (fd_pipe2surface(format) != FMT_INVALID)) {
- retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
- PIPE_BIND_VERTEX_BUFFER);
- }
-
- if ((usage & (PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED)) &&
- (fd_pipe2color(format) != COLORX_INVALID)) {
- retval |= usage & (PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED);
- }
-
- if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
- (fd_pipe2depth(format) != DEPTHX_INVALID)) {
- retval |= PIPE_BIND_DEPTH_STENCIL;
- }
-
- if ((usage & PIPE_BIND_INDEX_BUFFER) &&
- (fd_pipe2index(format) != INDEX_SIZE_INVALID)) {
- retval |= PIPE_BIND_INDEX_BUFFER;
- }
-
- if (usage & PIPE_BIND_TRANSFER_READ)
- retval |= PIPE_BIND_TRANSFER_READ;
- if (usage & PIPE_BIND_TRANSFER_WRITE)
- retval |= PIPE_BIND_TRANSFER_WRITE;
-
- if (retval != usage) {
- DBG("not supported: format=%s, target=%d, sample_count=%d, "
- "usage=%x, retval=%x", util_format_name(format),
- target, sample_count, usage, retval);
- }
-
- return retval == usage;
-}
-
boolean
fd_screen_bo_get_handle(struct pipe_screen *pscreen,
struct fd_bo *bo,
struct fd_screen *screen = fd_screen(pscreen);
struct fd_bo *bo;
+ if (whandle->type != DRM_API_HANDLE_TYPE_SHARED) {
+ DBG("Attempt to import unsupported handle type %d", whandle->type);
+ return NULL;
+ }
+
bo = fd_bo_from_name(screen->dev, whandle->handle);
if (!bo) {
DBG("ref name 0x%08x failed", whandle->handle);
fd_mesa_debug = debug_get_option_fd_mesa_debug();
+ if (fd_mesa_debug & FD_DBG_NOBIN)
+ fd_binning_enabled = false;
+
+ glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130);
+
if (!screen)
return NULL;
}
screen->device_id = val;
+ if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
+ DBG("could not get gpu-id");
+ goto fail;
+ }
+ screen->gpu_id = val;
+
+ /* explicitly checking for GPU revisions that are known to work. This
+ * may be overly conservative for a3xx, where spoofing the gpu_id with
+ * the blob driver seems to generate identical cmdstream dumps. But
+ * on a2xx, there seem to be small differences between the GPU revs
+ * so it is probably better to actually test first on real hardware
+ * before enabling:
+ *
+ * If you have a different adreno version, feel free to add it to one
+ * of the two cases below and see what happens. And if it works, please
+ * send a patch ;-)
+ */
+ switch (screen->gpu_id) {
+ case 220:
+ fd2_screen_init(pscreen);
+ break;
+ case 320:
+ case 330:
+ fd3_screen_init(pscreen);
+ break;
+ default:
+ debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
+ goto fail;
+ }
pscreen->destroy = fd_screen_destroy;
pscreen->get_param = fd_screen_get_param;
pscreen->get_paramf = fd_screen_get_paramf;
pscreen->get_shader_param = fd_screen_get_shader_param;
- pscreen->context_create = fd_context_create;
- pscreen->is_format_supported = fd_screen_is_format_supported;
fd_resource_screen_init(pscreen);
+ fd_query_screen_init(pscreen);
pscreen->get_name = fd_screen_get_name;
pscreen->get_vendor = fd_screen_get_vendor;