gallium: Add PIPE_SHADER_CAP_FP16
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
index 57010d64587f76b072420053e431cd7e4ff9b311..a91e3c2e709e133f44caf8f1a4d5b561e4afb3fc 100644 (file)
@@ -75,10 +75,10 @@ static const struct debug_named_value debug_options[] = {
                {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
                {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
                {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
-               {"nir",       FD_DBG_NIR,    "Prefer NIR as native IR"},
                {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
                {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
                {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
+               {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
                DEBUG_NAMED_VALUE_END
 };
 
@@ -217,10 +217,15 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
        case PIPE_CAP_FAKE_SW_MSAA:
        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
-       case PIPE_CAP_DEPTH_CLIP_DISABLE:
        case PIPE_CAP_CLIP_HALFZ:
                return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
 
+       case PIPE_CAP_DEPTH_CLIP_DISABLE:
+               return is_a3xx(screen) || is_a4xx(screen);
+
+       case PIPE_CAP_POLYGON_OFFSET_CLAMP:
+               return is_a5xx(screen);
+
        case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
                return 0;
        case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
@@ -274,7 +279,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MULTI_DRAW_INDIRECT:
        case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
        case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
-       case PIPE_CAP_POLYGON_OFFSET_CLAMP:
        case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
        case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
        case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
@@ -313,6 +317,14 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
        case PIPE_CAP_TGSI_BALLOT:
        case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+       case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
+       case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
+       case PIPE_CAP_POST_DEPTH_COVERAGE:
+       case PIPE_CAP_BINDLESS_TEXTURE:
+       case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
+       case PIPE_CAP_QUERY_SO_OVERFLOW:
+       case PIPE_CAP_MEMOBJ:
+       case PIPE_CAP_LOAD_CONSTBUF:
                return 0;
 
        case PIPE_CAP_MAX_VIEWPORTS:
@@ -376,7 +388,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_QUERY_TIMESTAMP:
        case PIPE_CAP_QUERY_TIME_ELAPSED:
                /* only a4xx, requires new enough kernel so we know max_freq: */
-               return (screen->max_freq > 0) && is_a4xx(screen);
+               return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen));
 
        case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
        case PIPE_CAP_MIN_TEXEL_OFFSET:
@@ -515,22 +527,15 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
                if (glsl120)
                        return 0;
                return is_ir3(screen) ? 1 : 0;
+       case PIPE_SHADER_CAP_FP16:
+               return 0;
        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
                return 16;
        case PIPE_SHADER_CAP_PREFERRED_IR:
-               switch (shader) {
-               case PIPE_SHADER_FRAGMENT:
-               case PIPE_SHADER_VERTEX:
-                       if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen))
-                               return PIPE_SHADER_IR_NIR;
-                       return PIPE_SHADER_IR_TGSI;
-               default:
-                       /* tgsi_to_nir doesn't really support much beyond FS/VS: */
-                       debug_assert(is_ir3(screen));
+               if (is_ir3(screen))
                        return PIPE_SHADER_IR_NIR;
-               }
-               break;
+               return PIPE_SHADER_IR_TGSI;
        case PIPE_SHADER_CAP_SUPPORTED_IRS:
                if (is_ir3(screen)) {
                        return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
@@ -671,7 +676,7 @@ fd_get_compiler_options(struct pipe_screen *pscreen,
        struct fd_screen *screen = fd_screen(pscreen);
 
        if (is_ir3(screen))
-               return ir3_get_compiler_options();
+               return ir3_get_compiler_options(screen->compiler);
 
        return NULL;
 }
@@ -835,9 +840,11 @@ fd_screen_create(struct fd_device *dev)
        if (screen->gpu_id >= 500) {
                screen->gmem_alignw = 64;
                screen->gmem_alignh = 32;
+               screen->num_vsc_pipes = 16;
        } else {
                screen->gmem_alignw = 32;
                screen->gmem_alignh = 32;
+               screen->num_vsc_pipes = 8;
        }
 
        /* NOTE: don't enable reordering on a2xx, since completely untested.