freedreno: Add debug flag for forcing linear layouts

[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 3ee73c2c496c4ceb82d84614da2d5a25c3de1854..d467cae6b002ea281e86358bb12cb650f96593fb 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -31,8 +31,8 @@
 
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_format_s3tc.h"
+#include "util/format/u_format.h"
+#include "util/format/u_format_s3tc.h"
 #include "util/u_screen.h"
 #include "util/u_string.h"
 #include "util/u_debug.h"
@@ -74,6 +74,7 @@ static const struct debug_named_value debug_options[] = {
                {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
                {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
                {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
+               {"nogmem",    FD_DBG_NOGMEM,  "Disable GMEM rendering (bypass only)"},
                {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
                {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
                {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
@@ -81,13 +82,15 @@ static const struct debug_named_value debug_options[] = {
                {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
                {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
                {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
-               {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
+               {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx)"},
                {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
                {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
                {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
                {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a2xx/a3xx/a5xx)"},
                {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
                {"noubwc",    FD_DBG_NOUBWC, "Disable UBWC for all internal buffers"},
+               {"nolrz",     FD_DBG_NOLRZ,  "Disable LRZ (a6xx)"},
+               {"notile",    FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
                DEBUG_NAMED_VALUE_END
 };
 
@@ -317,9 +320,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                if (is_a6xx(screen)) return 1;
                return 0;
 
-       case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
-               return 0;
-
        case PIPE_CAP_CONTEXT_PRIORITY_MASK:
                return screen->priority_mask;
 
@@ -345,6 +345,16 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_MAX_VARYINGS:
                return 16;
 
+       case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+               /* We don't really have a limit on this, it all goes into the main
+                * memory buffer. Needs to be at least 120 / 4 (minimum requirement
+                * for GL_MAX_TESS_PATCH_COMPONENTS).
+                */
+               return 128;
+
+       case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+               return 64 * 1024 * 1024;
+
        case PIPE_CAP_SHAREABLE_SHADERS:
        case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
        /* manage the variants for these ourself, to avoid breaking precompile: */
@@ -470,6 +480,8 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_FRAGMENT:
        case PIPE_SHADER_VERTEX:
                break;
+       case PIPE_SHADER_TESS_CTRL:
+       case PIPE_SHADER_TESS_EVAL:
        case PIPE_SHADER_GEOMETRY:
                if (is_a6xx(screen))
                        break;
@@ -513,8 +525,11 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
                 * everything is just normal registers.  This is just temporary
                 * hack until load_input/store_output handle arrays in a similar
                 * way as load_var/store_var..
+                *
+                * For tessellation stages, inputs are loaded using ldlw or ldg, both
+                * of which support indirection.
                 */
-               return 0;
+               return shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL;
        case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
        case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
                /* a2xx compiler doesn't handle indirect: */
@@ -906,6 +921,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
                break;
        case 618:
        case 630:
+       case 640:
                fd6_screen_init(pscreen);
                break;
        default:
@@ -927,6 +943,11 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
                screen->num_vsc_pipes = 8;
        }
 
+       if (fd_mesa_debug & FD_DBG_PERFC) {
+               screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
+                               &screen->num_perfcntr_groups);
+       }
+
        /* NOTE: don't enable if we have too old of a kernel to support
         * growable cmdstream buffers, since memory requirement for cmdstream
         * buffers would be too much otherwise.