freedreno: add adreno 650

[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index 6c66d56dd78bf8f6ad59535f83c1d69f0506d66c..e1c5b81cb32811de8d3730545deba39880190a45 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -61,9 +61,6 @@
 #include "ir3/ir3_nir.h"
 #include "a2xx/ir2.h"
 
-/* XXX this should go away */
-#include "state_tracker/drm_driver.h"
-
 static const struct debug_named_value debug_options[] = {
                {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
                {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly (a2xx only, see IR3_SHADER_DEBUG)"},
@@ -72,10 +69,10 @@ static const struct debug_named_value debug_options[] = {
                {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
                {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
                {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
-               {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
+               {"log",       FD_DBG_LOG,    "Enable GPU timestamp based logging (a6xx+)"},
                {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
                {"nogmem",    FD_DBG_NOGMEM,  "Disable GMEM rendering (bypass only)"},
-               {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
+               /* BIT(10) */
                {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
                {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
                {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
@@ -93,6 +90,7 @@ static const struct debug_named_value debug_options[] = {
                {"notile",    FD_DBG_NOTILE, "Disable tiling for all internal buffers"},
                {"layout",    FD_DBG_LAYOUT, "Dump resource layouts"},
                {"nofp16",    FD_DBG_NOFP16, "Disable mediump precision lowering"},
+               {"nohw",      FD_DBG_NOHW,   "Disable submitting commands to the HW"},
                DEBUG_NAMED_VALUE_END
 };
 
@@ -100,7 +98,6 @@ DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
 
 int fd_mesa_debug = 0;
 bool fd_binning_enabled = true;
-static bool glsl120 = false;
 
 static const char *
 fd_screen_get_name(struct pipe_screen *pscreen)
@@ -160,7 +157,7 @@ fd_screen_destroy(struct pipe_screen *pscreen)
 
        slab_destroy_parent(&screen->transfer_pool);
 
-       mtx_destroy(&screen->lock);
+       simple_mtx_destroy(&screen->lock);
 
        ralloc_free(screen->compiler);
 
@@ -191,9 +188,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_SEAMLESS_CUBE_MAP:
        case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
        case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
-       case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
-       case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
-       case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
        case PIPE_CAP_STRING_MARKER:
        case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
@@ -202,6 +196,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
                return 1;
 
+       case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
+       case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
+       case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
+               return !is_a2xx(screen);
+
        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
                return is_a2xx(screen);
        case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
@@ -294,8 +293,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
        case PIPE_CAP_GLSL_FEATURE_LEVEL:
        case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
-               if (glsl120)
-                       return 120;
                return is_ir3(screen) ? 140 : 120;
 
        case PIPE_CAP_ESSL_FEATURE_LEVEL:
@@ -406,9 +403,15 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
        /* Texturing. */
        case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
-               return 1 << (MAX_MIP_LEVELS - 1);
+               if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+                       return 16384;
+               else
+                       return 8192;
        case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-               return MAX_MIP_LEVELS;
+               if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
+                       return 15;
+               else
+                       return 14;
        case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
                return 11;
 
@@ -559,13 +562,13 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen,
        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
                return 1;
        case PIPE_SHADER_CAP_INTEGERS:
-               if (glsl120)
-                       return 0;
                return is_ir3(screen) ? 1 : 0;
        case PIPE_SHADER_CAP_INT64_ATOMICS:
                return 0;
        case PIPE_SHADER_CAP_FP16:
                return ((is_a5xx(screen) || is_a6xx(screen)) &&
+                               (shader == PIPE_SHADER_COMPUTE ||
+                                       shader == PIPE_SHADER_FRAGMENT) &&
                                !(fd_mesa_debug & FD_DBG_NOFP16));
        case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
        case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
@@ -805,8 +808,6 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        if (fd_mesa_debug & FD_DBG_NOBIN)
                fd_binning_enabled = false;
 
-       glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
-
        if (!screen)
                return NULL;
 
@@ -922,6 +923,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        case 330:
                fd3_screen_init(pscreen);
                break;
+       case 405:
        case 420:
        case 430:
                fd4_screen_init(pscreen);
@@ -934,6 +936,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        case 618:
        case 630:
        case 640:
+       case 650:
                fd6_screen_init(pscreen);
                break;
        default:
@@ -942,16 +945,18 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
        }
 
        if (screen->gpu_id >= 600) {
-               screen->gmem_alignw = 32;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = 16;
+               screen->gmem_alignh = 4;
+               screen->tile_alignw = is_a650(screen) ? 96 : 32;
+               screen->tile_alignh = 32;
                screen->num_vsc_pipes = 32;
        } else if (screen->gpu_id >= 500) {
-               screen->gmem_alignw = 64;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = screen->tile_alignw = 64;
+               screen->gmem_alignh = screen->tile_alignh = 32;
                screen->num_vsc_pipes = 16;
        } else {
-               screen->gmem_alignw = 32;
-               screen->gmem_alignh = 32;
+               screen->gmem_alignw = screen->tile_alignw = 32;
+               screen->gmem_alignh = screen->tile_alignh = 32;
                screen->num_vsc_pipes = 8;
        }
 
@@ -969,7 +974,9 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
 
        fd_bc_init(&screen->batch_cache);
 
-       (void) mtx_init(&screen->lock, mtx_plain);
+       list_inithead(&screen->context_list);
+
+       (void) simple_mtx_init(&screen->lock, mtx_plain);
 
        pscreen->destroy = fd_screen_destroy;
        pscreen->get_param = fd_screen_get_param;