freedreno/ir3: fix sam argument order comment
[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.c
index a4699e4b69e53921c5df77e1635b59d5d114e3c8..fe724442c0720f3e9449e632a90bc92e2b1721d6 100644 (file)
@@ -67,7 +67,7 @@ static const struct debug_named_value debug_options[] = {
                {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
                {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
                {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
-               {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizater debug messages"},
+               {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
                {"optdump",   FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"},
                {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 120 (rather than 130) on a3xx+"},
                {"nocp",      FD_DBG_NOCP,   "Disable copy-propagation"},
@@ -95,6 +95,13 @@ fd_screen_get_vendor(struct pipe_screen *pscreen)
        return "freedreno";
 }
 
+static const char *
+fd_screen_get_device_vendor(struct pipe_screen *pscreen)
+{
+       return "Qualcomm";
+}
+
+
 static uint64_t
 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 {
@@ -172,6 +179,10 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
        case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
                return is_a3xx(screen) || is_a4xx(screen);
 
+       case PIPE_CAP_INDEP_BLEND_ENABLE:
+       case PIPE_CAP_INDEP_BLEND_FUNC:
+               return is_a3xx(screen);
+
        case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
                return 256;
 
@@ -181,8 +192,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                return (is_a3xx(screen) || is_a4xx(screen)) ? 130 : 120;
 
        /* Unsupported features. */
-       case PIPE_CAP_INDEP_BLEND_ENABLE:
-       case PIPE_CAP_INDEP_BLEND_FUNC:
        case PIPE_CAP_DEPTH_CLIP_DISABLE:
        case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
        case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@@ -243,7 +252,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 
        /* Render targets. */
        case PIPE_CAP_MAX_RENDER_TARGETS:
-               return 1;
+               return screen->max_rts;
 
        /* Queries. */
        case PIPE_CAP_QUERY_TIME_ELAPSED:
@@ -293,7 +302,7 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
        case PIPE_CAPF_MAX_POINT_WIDTH:
        case PIPE_CAPF_MAX_POINT_WIDTH_AA:
-               return 8192.0f;
+               return 4092.0f;
        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
                return 16.0f;
        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
@@ -363,6 +372,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
        case PIPE_SHADER_CAP_DOUBLES:
        case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
                return 0;
        case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
                return 1;
@@ -530,6 +540,7 @@ fd_screen_create(struct fd_device *dev)
 
        pscreen->get_name = fd_screen_get_name;
        pscreen->get_vendor = fd_screen_get_vendor;
+       pscreen->get_device_vendor = fd_screen_get_device_vendor;
 
        pscreen->get_timestamp = fd_screen_get_timestamp;