freedreno: add renderonly scanout

[mesa.git] / src / gallium / drivers / freedreno / freedreno_screen.h

diff --git a/src/gallium/drivers/freedreno/freedreno_screen.h b/src/gallium/drivers/freedreno/freedreno_screen.h
index 55537f2d1c47f049d76d85a527b50f2ee372f594..7c457399f2a50a2ebf0068890846b3949092de47 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_screen.h
+++ b/src/gallium/drivers/freedreno/freedreno_screen.h
@@ -1,5 +1,3 @@
-/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
-
 /*
  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
  *
@@ -29,15 +27,17 @@
 #ifndef FREEDRENO_SCREEN_H_
 #define FREEDRENO_SCREEN_H_
 
-#include <freedreno_drmif.h>
-#include <freedreno_ringbuffer.h>
+#include "drm/freedreno_drmif.h"
+#include "drm/freedreno_ringbuffer.h"
 
 #include "pipe/p_screen.h"
 #include "util/u_memory.h"
 #include "util/slab.h"
 #include "os/os_thread.h"
+#include "renderonly/renderonly.h"
 
 #include "freedreno_batch_cache.h"
+#include "freedreno_perfcntr.h"
 #include "freedreno_util.h"
 
 struct fd_bo;
@@ -64,12 +64,20 @@ struct fd_screen {
        uint32_t gpu_id;         /* 220, 305, etc */
        uint32_t chip_id;        /* coreid:8 majorrev:8 minorrev:8 patch:8 */
        uint32_t max_freq;
+       uint32_t ram_size;
        uint32_t max_rts;        /* max # of render targets */
        uint32_t gmem_alignw, gmem_alignh;
        uint32_t num_vsc_pipes;
        uint32_t priority_mask;
        bool has_timestamp;
 
+       unsigned num_perfcntr_groups;
+       const struct fd_perfcntr_group *perfcntr_groups;
+
+       /* generated at startup from the perfcntr groups: */
+       unsigned num_perfcntr_queries;
+       struct pipe_driver_query_info *perfcntr_queries;
+
        void *compiler;          /* currently unused for a2xx */
 
        struct fd_device *dev;
@@ -80,6 +88,7 @@ struct fd_screen {
         */
        struct fd_pipe *pipe;
 
+       uint32_t (*fill_ubwc_buffer_sizes)(struct fd_resource *rsc);
        uint32_t (*setup_slices)(struct fd_resource *rsc);
        unsigned (*tile_mode)(const struct pipe_resource *prsc);
 
@@ -88,6 +97,13 @@ struct fd_screen {
        struct fd_batch_cache batch_cache;
 
        bool reorder;
+
+       uint16_t rsc_seqno;
+
+       unsigned num_supported_modifiers;
+       const uint64_t *supported_modifiers;
+
+       struct renderonly *ro;
 };
 
 static inline struct fd_screen *
@@ -98,12 +114,20 @@ fd_screen(struct pipe_screen *pscreen)
 
 boolean fd_screen_bo_get_handle(struct pipe_screen *pscreen,
                struct fd_bo *bo,
+               struct renderonly_scanout *scanout,
                unsigned stride,
                struct winsys_handle *whandle);
 struct fd_bo * fd_screen_bo_from_handle(struct pipe_screen *pscreen,
                struct winsys_handle *whandle);
 
-struct pipe_screen * fd_screen_create(struct fd_device *dev);
+struct pipe_screen *
+fd_screen_create(struct fd_device *dev, struct renderonly *ro);
+
+static inline boolean
+is_a20x(struct fd_screen *screen)
+{
+       return (screen->gpu_id >= 200) && (screen->gpu_id < 210);
+}
 
 /* is a3xx patch revision 0? */
 /* TODO a306.0 probably doesn't need this.. be more clever?? */
@@ -131,11 +155,17 @@ is_a5xx(struct fd_screen *screen)
        return (screen->gpu_id >= 500) && (screen->gpu_id < 600);
 }
 
+static inline boolean
+is_a6xx(struct fd_screen *screen)
+{
+       return (screen->gpu_id >= 600) && (screen->gpu_id < 700);
+}
+
 /* is it using the ir3 compiler (shader isa introduced with a3xx)? */
 static inline boolean
 is_ir3(struct fd_screen *screen)
 {
-       return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen);
+       return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 }
 
 static inline bool