freedreno: Add a6xx backend

[mesa.git] / src / gallium / drivers / freedreno / freedreno_util.h

diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h
index 08bc5d7ba4a00675ca2ae90a5c7bfc475cf3e437..30e3c6a735fef456a57f94f414fc2c338206e148 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -59,8 +59,9 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
 #define A3XX_MAX_RENDER_TARGETS 4
 #define A4XX_MAX_RENDER_TARGETS 8
 #define A5XX_MAX_RENDER_TARGETS 8
+#define A6XX_MAX_RENDER_TARGETS 8
 
-#define MAX_RENDER_TARGETS A5XX_MAX_RENDER_TARGETS
+#define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS
 
 #define FD_DBG_MSGS     0x0001
 #define FD_DBG_DISASM   0x0002
@@ -76,10 +77,15 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
 #define FD_DBG_SHADERDB 0x0800
 #define FD_DBG_FLUSH    0x1000
 #define FD_DBG_DEQP     0x2000
-#define FD_DBG_NIR      0x4000
-#define FD_DBG_REORDER  0x8000
-#define FD_DBG_BSTAT   0x10000
-#define FD_DBG_NOGROW  0x20000
+#define FD_DBG_INORDER  0x4000
+#define FD_DBG_BSTAT    0x8000
+#define FD_DBG_NOGROW  0x10000
+#define FD_DBG_LRZ     0x20000
+#define FD_DBG_NOINDR  0x40000
+#define FD_DBG_NOBLIT  0x80000
+#define FD_DBG_HIPRIO 0x100000
+#define FD_DBG_TTILE  0x200000
+#define FD_DBG_PERFC  0x400000
 
 extern int fd_mesa_debug;
 extern bool fd_binning_enabled;
@@ -108,6 +114,19 @@ static inline uint32_t DRAW(enum pc_di_primtype prim_type,
                        (instances         << 24);
 }
 
+static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type,
+               enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
+               enum pc_di_vis_cull_mode vis_cull_mode,
+               uint16_t count)
+{
+       return (prim_type         << 0) |
+                       (source_select     << 6) |
+                       ((index_size & 1)  << 11) |
+                       ((index_size >> 1) << 13) |
+                       (vis_cull_mode     << 9) |
+                       (count         << 16);
+}
+
 /* for tracking cmdstream positions that need to be patched: */
 struct fd_cs_patch {
        uint32_t *cs;
@@ -179,7 +198,6 @@ fd_half_precision(struct pipe_framebuffer_state *pfb)
 #define LOG_DWORDS 0
 
 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx);
-static inline void emit_marker5(struct fd_ringbuffer *ring, int scratch_idx);
 
 static inline void
 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
@@ -248,6 +266,12 @@ OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
        });
 }
 
+static inline void
+OUT_RB(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
+{
+       fd_ringbuffer_emit_reloc_ring_full(ring, target, 0);
+}
+
 static inline void BEGIN_RING(struct fd_ringbuffer *ring, uint32_t ndwords)
 {
        if (ring->cur + ndwords >= ring->end)
@@ -339,6 +363,9 @@ OUT_WFI5(struct fd_ringbuffer *ring)
 static inline void
 __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target)
 {
+       if (target->cur == target->start)
+               return;
+
        unsigned count = fd_ringbuffer_cmd_count(target);
 
        debug_assert(__gpu_id(ring) < 500);
@@ -366,15 +393,10 @@ __OUT_IB(struct fd_ringbuffer *ring, bool prefetch, struct fd_ringbuffer *target
 static inline void
 __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 {
-       unsigned count = fd_ringbuffer_cmd_count(target);
+       if (target->cur == target->start)
+               return;
 
-       /* for debug after a lock up, write a unique counter value
-        * to scratch6 for each IB, to make it easier to match up
-        * register dumps to cmdstream.  The combination of IB and
-        * DRAW (scratch7) is enough to "triangulate" the particular
-        * draw that caused lockup.
-        */
-       emit_marker5(ring, 6);
+       unsigned count = fd_ringbuffer_cmd_count(target);
 
        for (unsigned i = 0; i < count; i++) {
                uint32_t dwords;
@@ -383,8 +405,6 @@ __OUT_IB5(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
                assert(dwords > 0);
                OUT_RING(ring, dwords);
        }
-
-       emit_marker5(ring, 6);
 }
 
 /* CP_SCRATCH_REG4 is used to hold base address for query results: */
@@ -405,21 +425,6 @@ emit_marker(struct fd_ringbuffer *ring, int scratch_idx)
        OUT_RING(ring, ++marker_cnt);
 }
 
-static inline void
-emit_marker5(struct fd_ringbuffer *ring, int scratch_idx)
-{
-       extern unsigned marker_cnt;
-//XXX  unsigned reg = REG_A5XX_CP_SCRATCH_REG(scratch_idx);
-       unsigned reg = 0x00000b78 + scratch_idx;
-       assert(reg != HW_QUERY_BASE_REG);
-       if (reg == HW_QUERY_BASE_REG)
-               return;
-       OUT_WFI5(ring);
-       OUT_PKT4(ring, reg, 1);
-       OUT_RING(ring, ++marker_cnt);
-       OUT_WFI5(ring);
-}
-
 /* helper to get numeric value from environment variable..  mostly
  * just leaving this here because it is helpful to brute-force figure
  * out unknown formats, etc, which blob driver does not support:
@@ -449,4 +454,43 @@ pack_rgba(enum pipe_format format, const float *rgba)
 #define foreach_bit(b, mask) \
        for (uint32_t _m = (mask); _m && ({(b) = u_bit_scan(&_m); 1;});)
 
+
+#define BIT(bit) (1u << bit)
+
+/*
+ * a3xx+ helpers:
+ */
+
+static inline enum a3xx_msaa_samples
+fd_msaa_samples(unsigned samples)
+{
+       switch (samples) {
+       default:
+               debug_assert(0);
+       case 1: return MSAA_ONE;
+       case 2: return MSAA_TWO;
+       case 4: return MSAA_FOUR;
+       }
+}
+
+/*
+ * a4xx+ helpers:
+ */
+
+static inline enum a4xx_state_block
+fd4_stage2shadersb(enum shader_t type)
+{
+       switch (type) {
+       case SHADER_VERTEX:
+               return SB4_VS_SHADER;
+       case SHADER_FRAGMENT:
+               return SB4_FS_SHADER;
+       case SHADER_COMPUTE:
+               return SB4_CS_SHADER;
+       default:
+               unreachable("bad shader type");
+               return ~0;
+       }
+}
+
 #endif /* FREEDRENO_UTIL_H_ */