freedreno/ir3: debug cleanup

[mesa.git] / src / gallium / drivers / freedreno / freedreno_util.h

diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h
index 479f255f6fc7e72c1859bb812ffdb69afb4b21fe..4a971d93e7c51880596fd298456193a2a3dce424 100644 (file)
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -84,8 +84,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
 #define FD_DBG_HIPRIO 0x100000
 #define FD_DBG_TTILE  0x200000
 #define FD_DBG_PERFC  0x400000
-#define FD_DBG_SOFTPIN 0x800000
-
+#define FD_DBG_NOUBWC 0x800000
 extern int fd_mesa_debug;
 extern bool fd_binning_enabled;
 
@@ -244,8 +243,8 @@ OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data,
  */
 
 static inline void
-OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
-               uint32_t offset, uint64_t or, int32_t shift)
+__out_reloc(struct fd_ringbuffer *ring, struct fd_bo *bo,
+               uint32_t offset, uint64_t or, int32_t shift, uint32_t flags)
 {
        if (LOG_DWORDS) {
                DBG("ring[%p]: OUT_RELOC   %04x:  %p+%u << %d", ring,
@@ -254,7 +253,7 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
        debug_assert(offset < fd_bo_size(bo));
        fd_ringbuffer_reloc(ring, &(struct fd_reloc){
                .bo = bo,
-               .flags = FD_RELOC_READ,
+               .flags = flags,
                .offset = offset,
                .or = or,
                .shift = shift,
@@ -262,23 +261,25 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
        });
 }
 
+static inline void
+OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo,
+               uint32_t offset, uint64_t or, int32_t shift)
+{
+       __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ);
+}
+
 static inline void
 OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo,
                uint32_t offset, uint64_t or, int32_t shift)
 {
-       if (LOG_DWORDS) {
-               DBG("ring[%p]: OUT_RELOCW  %04x:  %p+%u << %d", ring,
-                               (uint32_t)(ring->cur - ring->start), bo, offset, shift);
-       }
-       debug_assert(offset < fd_bo_size(bo));
-       fd_ringbuffer_reloc(ring, &(struct fd_reloc){
-               .bo = bo,
-               .flags = FD_RELOC_READ | FD_RELOC_WRITE,
-               .offset = offset,
-               .or = or,
-               .shift = shift,
-               .orhi = or >> 32,
-       });
+       __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_WRITE);
+}
+
+static inline void
+OUT_RELOCD(struct fd_ringbuffer *ring, struct fd_bo *bo,
+               uint32_t offset, uint64_t or, int32_t shift)
+{
+       __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_DUMP);
 }
 
 static inline void
@@ -478,6 +479,7 @@ fd4_stage2shadersb(gl_shader_stage type)
        case MESA_SHADER_FRAGMENT:
                return SB4_FS_SHADER;
        case MESA_SHADER_COMPUTE:
+       case MESA_SHADER_KERNEL:
                return SB4_CS_SHADER;
        default:
                unreachable("bad shader type");
@@ -485,4 +487,17 @@ fd4_stage2shadersb(gl_shader_stage type)
        }
 }
 
+static inline enum a4xx_index_size
+fd4_size2indextype(unsigned index_size)
+{
+       switch (index_size) {
+       case 1: return INDEX4_SIZE_8_BIT;
+       case 2: return INDEX4_SIZE_16_BIT;
+       case 4: return INDEX4_SIZE_32_BIT;
+       }
+       DBG("unsupported index size: %d", index_size);
+       assert(0);
+       return INDEX4_SIZE_32_BIT;
+}
+
 #endif /* FREEDRENO_UTIL_H_ */