freedreno/ir3: need different compiler options for a5xx
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_cmdline.c
index d749bfad817588f20468285fdb98a58347ef85cc..10cf9c4556841d90f4acf8eed69a2ca6b8620821 100644 (file)
@@ -59,6 +59,45 @@ static void dump_info(struct ir3_shader_variant *so, const char *str)
 
 int st_glsl_type_size(const struct glsl_type *type);
 
+static void
+insert_sorted(struct exec_list *var_list, nir_variable *new_var)
+{
+       nir_foreach_variable(var, var_list) {
+               if (var->data.location > new_var->data.location) {
+                       exec_node_insert_node_before(&var->node, &new_var->node);
+                       return;
+               }
+       }
+       exec_list_push_tail(var_list, &new_var->node);
+}
+
+static void
+sort_varyings(struct exec_list *var_list)
+{
+       struct exec_list new_list;
+       exec_list_make_empty(&new_list);
+       nir_foreach_variable_safe(var, var_list) {
+               exec_node_remove(&var->node);
+               insert_sorted(&new_list, var);
+       }
+       exec_list_move_nodes_to(&new_list, var_list);
+}
+
+static void
+fixup_varying_slots(struct exec_list *var_list)
+{
+       nir_foreach_variable(var, var_list) {
+               if (var->data.location >= VARYING_SLOT_VAR0) {
+                       var->data.location += 9;
+               } else if ((var->data.location >= VARYING_SLOT_TEX0) &&
+                               (var->data.location <= VARYING_SLOT_TEX7)) {
+                       var->data.location += VARYING_SLOT_VAR0 - VARYING_SLOT_TEX0;
+               }
+       }
+}
+
+static struct ir3_compiler *compiler;
+
 static nir_shader *
 load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
 {
@@ -72,7 +111,7 @@ load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
        if (!prog)
                errx(1, "couldn't parse `%s'", files[0]);
 
-       nir_shader *nir = glsl_to_nir(prog, stage, ir3_get_compiler_options());
+       nir_shader *nir = glsl_to_nir(prog, stage, ir3_get_compiler_options(compiler));
 
        standalone_compiler_cleanup(prog);
 
@@ -90,7 +129,38 @@ load_glsl(unsigned num_files, char* const* files, gl_shader_stage stage)
        NIR_PASS_V(nir, nir_lower_var_copies);
        NIR_PASS_V(nir, nir_lower_io_types);
 
-       // TODO nir_assign_var_locations??
+       switch (stage) {
+       case MESA_SHADER_VERTEX:
+               nir_assign_var_locations(&nir->inputs,
+                               &nir->num_inputs,
+                               st_glsl_type_size);
+
+               /* Re-lower global vars, to deal with any dead VS inputs. */
+               NIR_PASS_V(nir, nir_lower_global_vars_to_local);
+
+               sort_varyings(&nir->outputs);
+               nir_assign_var_locations(&nir->outputs,
+                               &nir->num_outputs,
+                               st_glsl_type_size);
+               fixup_varying_slots(&nir->outputs);
+               break;
+       case MESA_SHADER_FRAGMENT:
+               sort_varyings(&nir->inputs);
+               nir_assign_var_locations(&nir->inputs,
+                               &nir->num_inputs,
+                               st_glsl_type_size);
+               fixup_varying_slots(&nir->inputs);
+               nir_assign_var_locations(&nir->outputs,
+                               &nir->num_outputs,
+                               st_glsl_type_size);
+               break;
+       default:
+               errx(1, "unhandled shader stage: %d", stage);
+       }
+
+       nir_assign_var_locations(&nir->uniforms,
+                       &nir->num_uniforms,
+                       st_glsl_type_size);
 
        NIR_PASS_V(nir, nir_lower_system_values);
        NIR_PASS_V(nir, nir_lower_io, nir_var_all, st_glsl_type_size, 0);
@@ -298,6 +368,8 @@ int main(int argc, char **argv)
 
        nir_shader *nir;
 
+       compiler = ir3_compiler_create(NULL, gpu_id);
+
        if (s.from_tgsi) {
                struct tgsi_token toks[65536];
 
@@ -324,7 +396,7 @@ int main(int argc, char **argv)
                return -1;
        }
 
-       s.compiler = ir3_compiler_create(NULL, gpu_id);
+       s.compiler = compiler;
        s.nir = ir3_optimize_nir(&s, nir, NULL);
 
        v.key = key;