freedreno/ir3: Merge the redundant immediate_idx/immediates_count fields
[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_const.h
index ee73bc501d9665edbec8d97de4011a545c95794b..7a0386e3f3246239ad0305141bf1347d33aff211 100644 (file)
@@ -97,8 +97,8 @@ ir3_emit_user_consts(struct fd_screen *screen, const struct ir3_shader_variant *
        const struct ir3_ubo_analysis_state *state = &const_state->ubo_state;
 
        for (unsigned i = 0; i < state->num_enabled; i++) {
-               assert(!state->range[i].bindless);
-               unsigned ubo = state->range[i].block;
+               assert(!state->range[i].ubo.bindless);
+               unsigned ubo = state->range[i].ubo.block;
                if (!(constbuf->enabled_mask & (1 << ubo)))
                        continue;
                struct pipe_constant_buffer *cb = &constbuf->cb[ubo];
@@ -228,7 +228,7 @@ ir3_emit_image_dims(struct fd_screen *screen, const struct ir3_shader_variant *v
                                 * be the same, so use original dimensions for y and z
                                 * stride:
                                 */
-                               dims[off + 1] = slice->pitch;
+                               dims[off + 1] = fd_resource_pitch(rsc, img->u.tex.level);
                                /* see corresponding logic in fd_resource_offset(): */
                                if (rsc->layout.layer_first) {
                                        dims[off + 2] = rsc->layout.layer_size;
@@ -259,7 +259,7 @@ ir3_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v
 {
        const struct ir3_const_state *const_state = ir3_const_state(v);
        uint32_t base = const_state->offsets.immediate;
-       int size = const_state->immediates_count;
+       int size = DIV_ROUND_UP(const_state->immediates_count, 4);
 
        /* truncate size to avoid writing constants that shader
         * does not use:
@@ -447,15 +447,12 @@ ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
        const struct ir3_const_state *const_state = ir3_const_state(v);
        uint32_t offset = const_state->offsets.driver_param;
        uint32_t vertex_params[IR3_DP_VS_COUNT] = {
-                       [IR3_DP_VTXID_BASE] = info->index_size ?
+                       [IR3_DP_DRAWID]      = 0,  /* filled by hw (CP_DRAW_INDIRECT_MULTI) */
+                       [IR3_DP_VTXID_BASE]  = info->index_size ?
                                        info->index_bias : info->start,
-                                       [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
+                       [IR3_DP_INSTID_BASE] = info->start_instance,
+                       [IR3_DP_VTXCNT_MAX]  = max_tf_vtx(ctx, v),
        };
-       /* if no user-clip-planes, we don't need to emit the
-        * entire thing:
-        */
-       uint32_t vertex_params_size = 4;
-
        if (v->key.ucp_enables) {
                struct pipe_clip_state *ucp = &ctx->ucp;
                unsigned pos = IR3_DP_UCP0_X;
@@ -465,10 +462,16 @@ ir3_emit_vs_driver_params(const struct ir3_shader_variant *v,
                                pos++;
                        }
                }
-               vertex_params_size = ARRAY_SIZE(vertex_params);
        }
 
-       vertex_params_size = MAX2(vertex_params_size, const_state->num_driver_params);
+       /* Only emit as many params as needed, i.e. up to the highest enabled UCP
+        * plane. However a binning pass may drop even some of these, so limit to
+        * program max.
+        */
+       const uint32_t vertex_params_size = MIN2(
+                       const_state->num_driver_params,
+                       (v->constlen - offset) * 4);
+       assert(vertex_params_size <= IR3_DP_VS_COUNT);
 
        bool needs_vtxid_base =
                ir3_find_sysval_regid(v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) != regid(63, 0);