freedreno/a4xx: better workaround for astc+srgb

[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.c

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 7d17f426ad352553417e007d68ae69e9ca06cb2e..435a565e61ec1b8e9019084cc07dfcbb8bb94cad 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -127,14 +127,14 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 static void
 assemble_variant(struct ir3_shader_variant *v)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
-       uint32_t gpu_id = v->shader->compiler->gpu_id;
+       struct ir3_compiler *compiler = v->shader->compiler;
+       uint32_t gpu_id = compiler->gpu_id;
        uint32_t sz, *bin;
 
        bin = ir3_shader_assemble(v, gpu_id);
        sz = v->info.sizedwords * 4;
 
-       v->bo = fd_bo_new(ctx->dev, sz,
+       v->bo = fd_bo_new(compiler->dev, sz,
                        DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
                        DRM_FREEDRENO_GEM_TYPE_KMEM);
 
@@ -223,6 +223,7 @@ ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
                        key.vsaturate_s = 0;
                        key.vsaturate_t = 0;
                        key.vsaturate_r = 0;
+                       key.vastc_srgb = 0;
                }
                break;
        case SHADER_VERTEX:
@@ -233,6 +234,7 @@ ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
                        key.fsaturate_s = 0;
                        key.fsaturate_t = 0;
                        key.fsaturate_r = 0;
+                       key.fastc_srgb = 0;
                }
                break;
        }
@@ -266,14 +268,13 @@ ir3_shader_destroy(struct ir3_shader *shader)
 }
 
 struct ir3_shader *
-ir3_shader_create(struct pipe_context *pctx,
+ir3_shader_create(struct ir3_compiler *compiler,
                const struct pipe_shader_state *cso,
                enum shader_t type)
 {
        struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
-       shader->compiler = fd_context(pctx)->screen->compiler;
+       shader->compiler = compiler;
        shader->id = ++shader->compiler->shader_count;
-       shader->pctx = pctx;
        shader->type = type;
        if (fd_mesa_debug & FD_DBG_DISASM) {
                DBG("dump tgsi: type=%d", shader->type);
@@ -463,10 +464,9 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
 #include "freedreno_resource.h"
 
 static void
-emit_user_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
-               struct fd_constbuf_stateobj *constbuf)
+emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
+               struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
        const unsigned index = 0;     /* user consts are index 0 */
        /* TODO save/restore dirty_mask for binning pass instead: */
        uint32_t dirty_mask = constbuf->enabled_mask;
@@ -502,12 +502,11 @@ emit_user_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 }
 
 static void
-emit_ubos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
-               struct fd_constbuf_stateobj *constbuf)
+emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
+               struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
        uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
        if (v->constlen > offset) {
-               struct fd_context *ctx = fd_context(v->shader->pctx);
                uint32_t params = MIN2(4, v->constlen - offset) * 4;
                uint32_t offsets[params];
                struct fd_bo *bos[params];
@@ -532,9 +531,9 @@ emit_ubos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 }
 
 static void
-emit_immediates(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
+emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
+               struct fd_ringbuffer *ring)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
        int size = v->immediates_count;
        uint32_t base = v->first_immediate;
 
@@ -556,12 +555,12 @@ emit_immediates(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 
 /* emit stream-out buffers: */
 static void
-emit_tfbos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
+emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
+               struct fd_ringbuffer *ring)
 {
        /* streamout addresses after driver-params: */
        uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
        if (v->constlen > offset) {
-               struct fd_context *ctx = fd_context(v->shader->pctx);
                struct fd_streamout_stateobj *so = &ctx->streamout;
                struct pipe_stream_output_info *info = &v->shader->stream_output;
                uint32_t params = 4;
@@ -587,9 +586,8 @@ emit_tfbos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 }
 
 static uint32_t
-max_tf_vtx(struct ir3_shader_variant *v)
+max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
        struct fd_streamout_stateobj *so = &ctx->streamout;
        struct pipe_stream_output_info *info = &v->shader->stream_output;
        uint32_t maxvtxcnt = 0x7fffffff;
@@ -633,11 +631,9 @@ max_tf_vtx(struct ir3_shader_variant *v)
 }
 
 void
-ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
-               const struct pipe_draw_info *info, uint32_t dirty)
+ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+               struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty)
 {
-       struct fd_context *ctx = fd_context(v->shader->pctx);
-
        if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
                struct fd_constbuf_stateobj *constbuf;
                bool shader_dirty;
@@ -653,10 +649,10 @@ ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
                        return;
                }
 
-               emit_user_consts(v, ring, constbuf);
-               emit_ubos(v, ring, constbuf);
+               emit_user_consts(ctx, v, ring, constbuf);
+               emit_ubos(ctx, v, ring, constbuf);
                if (shader_dirty)
-                       emit_immediates(v, ring);
+                       emit_immediates(ctx, v, ring);
        }
 
        /* emit driver params every time: */
@@ -667,7 +663,7 @@ ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
                        uint32_t vertex_params[IR3_DP_COUNT] = {
                                [IR3_DP_VTXID_BASE] = info->indexed ?
                                                info->index_bias : info->start,
-                               [IR3_DP_VTXCNT_MAX] = max_tf_vtx(v),
+                               [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
                        };
                        /* if no user-clip-planes, we don't need to emit the
                         * entire thing:
@@ -692,7 +688,7 @@ ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 
                        /* if needed, emit stream-out buffer addresses: */
                        if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
-                               emit_tfbos(v, ring);
+                               emit_tfbos(ctx, v, ring);
                        }
                }
        }