freedreno/ir3: rework location of driver constants

[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.c

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 8920225be13ded39539dde4d3b9afb848e2faafc..4da7246a0cf3e0f3ba265d8283a3e9f2c2aa5f81 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -366,7 +366,7 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
        }
 
        for (i = 0; i < so->immediates_count; i++) {
-               debug_printf("@const(c%d.x)\t", so->first_immediate + i);
+               debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
                debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
                                so->immediates[i].val[0],
                                so->immediates[i].val[1],
@@ -503,7 +503,7 @@ emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
                 * the user consts early to avoid HLSQ lockup caused by
                 * writing too many consts
                 */
-               uint32_t max_const = MIN2(v->first_driver_param, v->constlen);
+               uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
 
                // I expect that size should be a multiple of vec4's:
                assert(size == align(size, 4));
@@ -527,9 +527,9 @@ static void
 emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
                struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 {
-       uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
+       uint32_t offset = v->constbase.ubo;
        if (v->constlen > offset) {
-               uint32_t params = MIN2(4, v->constlen - offset) * 4;
+               uint32_t params = v->num_ubos;
                uint32_t offsets[params];
                struct pipe_resource *prscs[params];
 
@@ -557,7 +557,7 @@ emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
                struct fd_ringbuffer *ring)
 {
        int size = v->immediates_count;
-       uint32_t base = v->first_immediate;
+       uint32_t base = v->constbase.immediate;
 
        /* truncate size to avoid writing constants that shader
         * does not use:
@@ -581,7 +581,7 @@ emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
                struct fd_ringbuffer *ring)
 {
        /* streamout addresses after driver-params: */
-       uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
+       uint32_t offset = v->constbase.tfbo;
        if (v->constlen > offset) {
                struct fd_streamout_stateobj *so = &ctx->streamout;
                struct pipe_stream_output_info *info = &v->shader->stream_output;
@@ -680,8 +680,8 @@ ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
        /* emit driver params every time: */
        /* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
        if (info && (v->type == SHADER_VERTEX)) {
-               uint32_t offset = v->first_driver_param + IR3_DRIVER_PARAM_OFF;
-               if (v->constlen >= offset) {
+               uint32_t offset = v->constbase.driver_param;
+               if (v->constlen > offset) {
                        uint32_t vertex_params[IR3_DP_COUNT] = {
                                [IR3_DP_VTXID_BASE] = info->indexed ?
                                                info->index_bias : info->start,