#include "ir3_compiler.h"
#include "ir3_nir.h"
+int
+ir3_glsl_type_size(const struct glsl_type *type)
+{
+ return glsl_count_attribute_slots(type, false);
+}
+
static void
delete_variant(struct ir3_shader_variant *v)
{
static void
assemble_variant(struct ir3_shader_variant *v)
{
- struct fd_context *ctx = fd_context(v->shader->pctx);
- uint32_t gpu_id = v->shader->compiler->gpu_id;
+ struct ir3_compiler *compiler = v->shader->compiler;
+ uint32_t gpu_id = compiler->gpu_id;
uint32_t sz, *bin;
bin = ir3_shader_assemble(v, gpu_id);
sz = v->info.sizedwords * 4;
- v->bo = fd_bo_new(ctx->dev, sz,
+ v->bo = fd_bo_new(compiler->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM);
ir3_shader_disasm(v, bin);
}
- if (fd_mesa_debug & FD_DBG_SHADERDB) {
- /* print generic shader info: */
- fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n",
- ir3_shader_stage(v->shader),
- v->shader->id, v->id,
- v->info.instrs_count,
- v->info.sizedwords);
- fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u half, %u full\n",
- ir3_shader_stage(v->shader),
- v->shader->id, v->id,
- v->info.max_half_reg + 1,
- v->info.max_reg + 1);
- fprintf(stderr, "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
- ir3_shader_stage(v->shader),
- v->shader->id, v->id,
- v->info.max_const + 1,
- v->constlen);
- }
-
free(bin);
/* no need to keep the ir around beyond this point: */
v->ir = NULL;
}
+static void
+dump_shader_info(struct ir3_shader_variant *v, struct pipe_debug_callback *debug)
+{
+ if (!unlikely(fd_mesa_debug & FD_DBG_SHADERDB))
+ return;
+
+ pipe_debug_message(debug, SHADER_INFO, "\n"
+ "SHADER-DB: %s prog %d/%d: %u instructions, %u dwords\n"
+ "SHADER-DB: %s prog %d/%d: %u half, %u full\n"
+ "SHADER-DB: %s prog %d/%d: %u const, %u constlen\n",
+ ir3_shader_stage(v->shader),
+ v->shader->id, v->id,
+ v->info.instrs_count,
+ v->info.sizedwords,
+ ir3_shader_stage(v->shader),
+ v->shader->id, v->id,
+ v->info.max_half_reg + 1,
+ v->info.max_reg + 1,
+ ir3_shader_stage(v->shader),
+ v->shader->id, v->id,
+ v->info.max_const + 1,
+ v->constlen);
+}
+
static struct ir3_shader_variant *
create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
{
}
struct ir3_shader_variant *
-ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
+ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key,
+ struct pipe_debug_callback *debug)
{
struct ir3_shader_variant *v;
*/
switch (shader->type) {
case SHADER_FRAGMENT:
- case SHADER_COMPUTE:
key.binning_pass = false;
if (key.has_per_samp) {
key.vsaturate_s = 0;
key.vsaturate_t = 0;
key.vsaturate_r = 0;
+ key.vastc_srgb = 0;
}
break;
case SHADER_VERTEX:
key.fsaturate_s = 0;
key.fsaturate_t = 0;
key.fsaturate_r = 0;
+ key.fastc_srgb = 0;
}
break;
+ default:
+ /* TODO */
+ break;
}
for (v = shader->variants; v; v = v->next)
if (v) {
v->next = shader->variants;
shader->variants = v;
+ dump_shader_info(v, debug);
}
return v;
}
struct ir3_shader *
-ir3_shader_create(struct pipe_context *pctx,
- const struct pipe_shader_state *cso,
- enum shader_t type)
+ir3_shader_create(struct ir3_compiler *compiler,
+ const struct pipe_shader_state *cso, enum shader_t type,
+ struct pipe_debug_callback *debug)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
- shader->compiler = fd_context(pctx)->screen->compiler;
+ shader->compiler = compiler;
shader->id = ++shader->compiler->shader_count;
- shader->pctx = pctx;
shader->type = type;
- if (fd_mesa_debug & FD_DBG_DISASM) {
- DBG("dump tgsi: type=%d", shader->type);
- tgsi_dump(cso->tokens, 0);
+
+ nir_shader *nir;
+ if (cso->type == PIPE_SHADER_IR_NIR) {
+ /* we take ownership of the reference: */
+ nir = cso->ir.nir;
+
+ NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
+ (nir_lower_io_options)0);
+ } else {
+ debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
+ if (fd_mesa_debug & FD_DBG_DISASM) {
+ DBG("dump tgsi: type=%d", shader->type);
+ tgsi_dump(cso->tokens, 0);
+ }
+ nir = ir3_tgsi_to_nir(cso->tokens);
}
- nir_shader *nir = ir3_tgsi_to_nir(cso->tokens);
/* do first pass optimization, ignoring the key: */
shader->nir = ir3_optimize_nir(shader, nir, NULL);
if (fd_mesa_debug & FD_DBG_DISASM) {
DBG("dump nir%d: type=%d", shader->id, shader->type);
nir_print_shader(shader->nir, stdout);
}
+
shader->stream_output = cso->stream_output;
if (fd_mesa_debug & FD_DBG_SHADERDB) {
/* if shader-db run, create a standard variant immediately
* (as otherwise nothing will trigger the shader to be
* actually compiled)
*/
- static struct ir3_shader_key key = {0};
- ir3_shader_variant(shader, key);
+ static struct ir3_shader_key key;
+ memset(&key, 0, sizeof(key));
+ ir3_shader_variant(shader, key, debug);
+ }
+ return shader;
+}
+
+/* a bit annoying that compute-shader and normal shader state objects
+ * aren't a bit more aligned.
+ */
+struct ir3_shader *
+ir3_shader_create_compute(struct ir3_compiler *compiler,
+ const struct pipe_compute_state *cso,
+ struct pipe_debug_callback *debug)
+{
+ struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
+
+ shader->compiler = compiler;
+ shader->id = ++shader->compiler->shader_count;
+ shader->type = SHADER_COMPUTE;
+
+ nir_shader *nir;
+ if (cso->ir_type == PIPE_SHADER_IR_NIR) {
+ /* we take ownership of the reference: */
+ nir = (nir_shader *)cso->prog;
+
+ NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
+ (nir_lower_io_options)0);
+ } else {
+ debug_assert(cso->ir_type == PIPE_SHADER_IR_TGSI);
+ if (fd_mesa_debug & FD_DBG_DISASM) {
+ DBG("dump tgsi: type=%d", shader->type);
+ tgsi_dump(cso->prog, 0);
+ }
+ nir = ir3_tgsi_to_nir(cso->prog);
+ }
+
+ /* do first pass optimization, ignoring the key: */
+ shader->nir = ir3_optimize_nir(shader, nir, NULL);
+ if (fd_mesa_debug & FD_DBG_DISASM) {
+ DBG("dump nir%d: type=%d", shader->id, shader->type);
+ nir_print_shader(shader->nir, stdout);
}
+
return shader;
}
}
for (i = 0; i < so->immediates_count; i++) {
- debug_printf("@const(c%d.x)\t", so->first_immediate + i);
+ debug_printf("@const(c%d.x)\t", so->constbase.immediate + i);
debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
so->immediates[i].val[0],
so->immediates[i].val[1],
}
debug_printf("\n");
break;
- case SHADER_COMPUTE:
+ default:
+ /* TODO */
break;
}
if (so->frag_face)
debug_printf("; fragface: hr0.x\n");
break;
- case SHADER_COMPUTE:
+ default:
+ /* TODO */
break;
}
debug_printf("\n");
}
+uint64_t
+ir3_shader_outputs(const struct ir3_shader *so)
+{
+ return so->nir->info.outputs_written;
+}
+
/* This has to reach into the fd_context a bit more than the rest of
* ir3, but it needs to be aligned with the compiler, so both agree
* on which const regs hold what. And the logic is identical between
#include "freedreno_resource.h"
static void
-emit_user_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
- struct fd_constbuf_stateobj *constbuf)
+emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{
- struct fd_context *ctx = fd_context(v->shader->pctx);
const unsigned index = 0; /* user consts are index 0 */
/* TODO save/restore dirty_mask for binning pass instead: */
uint32_t dirty_mask = constbuf->enabled_mask;
* the user consts early to avoid HLSQ lockup caused by
* writing too many consts
*/
- uint32_t max_const = MIN2(v->first_driver_param, v->constlen);
+ uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
// I expect that size should be a multiple of vec4's:
assert(size == align(size, 4));
size = MIN2(size, 4 * max_const);
if (size > 0) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, v->type, 0,
cb->buffer_offset, size,
cb->user_buffer, cb->buffer);
}
static void
-emit_ubos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
- struct fd_constbuf_stateobj *constbuf)
+emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{
- uint32_t offset = v->first_driver_param + IR3_UBOS_OFF;
+ uint32_t offset = v->constbase.ubo;
if (v->constlen > offset) {
- struct fd_context *ctx = fd_context(v->shader->pctx);
- uint32_t params = MIN2(4, v->constlen - offset) * 4;
+ uint32_t params = v->num_ubos;
uint32_t offsets[params];
- struct fd_bo *bos[params];
+ struct pipe_resource *prscs[params];
for (uint32_t i = 0; i < params; i++) {
const uint32_t index = i + 1; /* UBOs start at index 1 */
if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
offsets[i] = cb->buffer_offset;
- bos[i] = fd_resource(cb->buffer)->bo;
+ prscs[i] = cb->buffer;
} else {
offsets[i] = 0;
- bos[i] = NULL;
+ prscs[i] = NULL;
}
}
- fd_wfi(ctx, ring);
- ctx->emit_const_bo(ring, v->type, false, offset * 4, params, bos, offsets);
+ fd_wfi(ctx->batch, ring);
+ ctx->emit_const_bo(ring, v->type, false, offset * 4, params, prscs, offsets);
}
}
static void
-emit_immediates(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
+emit_ssbo_sizes(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb)
+{
+ uint32_t offset = v->constbase.ssbo_sizes;
+ if (v->constlen > offset) {
+ uint32_t sizes[align(v->const_layout.ssbo_size.count, 4)];
+ unsigned mask = v->const_layout.ssbo_size.mask;
+
+ while (mask) {
+ unsigned index = u_bit_scan(&mask);
+ unsigned off = v->const_layout.ssbo_size.off[index];
+ sizes[off] = sb->sb[index].buffer_size;
+ }
+
+ fd_wfi(ctx->batch, ring);
+ ctx->emit_const(ring, v->type, offset * 4,
+ 0, ARRAY_SIZE(sizes), sizes, NULL);
+ }
+}
+
+static void
+emit_image_dims(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si)
+{
+ uint32_t offset = v->constbase.image_dims;
+ if (v->constlen > offset) {
+ uint32_t dims[align(v->const_layout.image_dims.count, 4)];
+ unsigned mask = v->const_layout.image_dims.mask;
+
+ while (mask) {
+ struct pipe_image_view *img;
+ struct fd_resource *rsc;
+ unsigned index = u_bit_scan(&mask);
+ unsigned off = v->const_layout.image_dims.off[index];
+
+ img = &si->si[index];
+ rsc = fd_resource(img->resource);
+
+ dims[off + 0] = rsc->cpp;
+ if (img->resource->target != PIPE_BUFFER) {
+ unsigned lvl = img->u.tex.level;
+ dims[off + 1] = rsc->slices[lvl].pitch * rsc->cpp;
+ dims[off + 2] = rsc->slices[lvl].size0;
+ }
+ }
+
+ fd_wfi(ctx->batch, ring);
+ ctx->emit_const(ring, v->type, offset * 4,
+ 0, ARRAY_SIZE(dims), dims, NULL);
+ }
+}
+
+static void
+emit_immediates(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring)
{
- struct fd_context *ctx = fd_context(v->shader->pctx);
int size = v->immediates_count;
- uint32_t base = v->first_immediate;
+ uint32_t base = v->constbase.immediate;
/* truncate size to avoid writing constants that shader
* does not use:
size *= 4;
if (size > 0) {
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, v->type, base,
0, size, v->immediates[0].val, NULL);
}
/* emit stream-out buffers: */
static void
-emit_tfbos(struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
+emit_tfbos(struct fd_context *ctx, const struct ir3_shader_variant *v,
+ struct fd_ringbuffer *ring)
{
/* streamout addresses after driver-params: */
- uint32_t offset = v->first_driver_param + IR3_TFBOS_OFF;
+ uint32_t offset = v->constbase.tfbo;
if (v->constlen > offset) {
- struct fd_context *ctx = fd_context(v->shader->pctx);
struct fd_streamout_stateobj *so = &ctx->streamout;
struct pipe_stream_output_info *info = &v->shader->stream_output;
uint32_t params = 4;
uint32_t offsets[params];
- struct fd_bo *bos[params];
+ struct pipe_resource *prscs[params];
for (uint32_t i = 0; i < params; i++) {
struct pipe_stream_output_target *target = so->targets[i];
if (target) {
offsets[i] = (so->offsets[i] * info->stride[i] * 4) +
target->buffer_offset;
- bos[i] = fd_resource(target->buffer)->bo;
+ prscs[i] = target->buffer;
} else {
offsets[i] = 0;
- bos[i] = NULL;
+ prscs[i] = NULL;
}
}
- fd_wfi(ctx, ring);
- ctx->emit_const_bo(ring, v->type, true, offset * 4, params, bos, offsets);
+ fd_wfi(ctx->batch, ring);
+ ctx->emit_const_bo(ring, v->type, true, offset * 4, params, prscs, offsets);
}
}
static uint32_t
-max_tf_vtx(struct ir3_shader_variant *v)
+max_tf_vtx(struct fd_context *ctx, const struct ir3_shader_variant *v)
{
- struct fd_context *ctx = fd_context(v->shader->pctx);
struct fd_streamout_stateobj *so = &ctx->streamout;
struct pipe_stream_output_info *info = &v->shader->stream_output;
uint32_t maxvtxcnt = 0x7fffffff;
+ if (ctx->screen->gpu_id >= 500)
+ return 0;
if (v->key.binning_pass)
return 0;
if (v->shader->stream_output.num_outputs == 0)
return maxvtxcnt;
}
-void
-ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
- const struct pipe_draw_info *info, uint32_t dirty)
+static void
+emit_common_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+ struct fd_context *ctx, enum pipe_shader_type t)
{
- struct fd_context *ctx = fd_context(v->shader->pctx);
+ enum fd_dirty_shader_state dirty = ctx->dirty_shader[t];
- if (dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) {
+ if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_CONST)) {
struct fd_constbuf_stateobj *constbuf;
bool shader_dirty;
- if (v->type == SHADER_VERTEX) {
- constbuf = &ctx->constbuf[PIPE_SHADER_VERTEX];
- shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_VP);
- } else if (v->type == SHADER_FRAGMENT) {
- constbuf = &ctx->constbuf[PIPE_SHADER_FRAGMENT];
- shader_dirty = !!(ctx->prog.dirty & FD_SHADER_DIRTY_FP);
- } else {
- unreachable("bad shader type");
- return;
- }
+ constbuf = &ctx->constbuf[t];
+ shader_dirty = !!(dirty & FD_DIRTY_SHADER_PROG);
- emit_user_consts(v, ring, constbuf);
- emit_ubos(v, ring, constbuf);
+ emit_user_consts(ctx, v, ring, constbuf);
+ emit_ubos(ctx, v, ring, constbuf);
if (shader_dirty)
- emit_immediates(v, ring);
+ emit_immediates(ctx, v, ring);
}
+ if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_SSBO)) {
+ struct fd_shaderbuf_stateobj *sb = &ctx->shaderbuf[t];
+ emit_ssbo_sizes(ctx, v, ring, sb);
+ }
+
+ if (dirty & (FD_DIRTY_SHADER_PROG | FD_DIRTY_SHADER_IMAGE)) {
+ struct fd_shaderimg_stateobj *si = &ctx->shaderimg[t];
+ emit_image_dims(ctx, v, ring, si);
+ }
+}
+
+void
+ir3_emit_vs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+ struct fd_context *ctx, const struct pipe_draw_info *info)
+{
+ debug_assert(v->type == SHADER_VERTEX);
+
+ emit_common_consts(v, ring, ctx, PIPE_SHADER_VERTEX);
+
/* emit driver params every time: */
/* TODO skip emit if shader doesn't use driver params to avoid WFI.. */
- if (info && (v->type == SHADER_VERTEX)) {
- uint32_t offset = v->first_driver_param + IR3_DRIVER_PARAM_OFF;
- if (v->constlen >= offset) {
- uint32_t vertex_params[IR3_DP_COUNT] = {
- [IR3_DP_VTXID_BASE] = info->indexed ?
+ if (info) {
+ uint32_t offset = v->constbase.driver_param;
+ if (v->constlen > offset) {
+ uint32_t vertex_params[IR3_DP_VS_COUNT] = {
+ [IR3_DP_VTXID_BASE] = info->index_size ?
info->index_bias : info->start,
- [IR3_DP_VTXCNT_MAX] = max_tf_vtx(v),
+ [IR3_DP_VTXCNT_MAX] = max_tf_vtx(ctx, v),
};
/* if no user-clip-planes, we don't need to emit the
* entire thing:
vertex_params_size = ARRAY_SIZE(vertex_params);
}
- fd_wfi(ctx, ring);
+ fd_wfi(ctx->batch, ring);
ctx->emit_const(ring, SHADER_VERTEX, offset * 4, 0,
vertex_params_size, vertex_params, NULL);
/* if needed, emit stream-out buffer addresses: */
if (vertex_params[IR3_DP_VTXCNT_MAX] > 0) {
- emit_tfbos(v, ring);
+ emit_tfbos(ctx, v, ring);
}
}
}
}
+
+void
+ir3_emit_fs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+ struct fd_context *ctx)
+{
+ debug_assert(v->type == SHADER_FRAGMENT);
+
+ emit_common_consts(v, ring, ctx, PIPE_SHADER_FRAGMENT);
+}
+
+/* emit compute-shader consts: */
+void
+ir3_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+ struct fd_context *ctx, const struct pipe_grid_info *info)
+{
+ debug_assert(v->type == SHADER_COMPUTE);
+
+ emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
+
+ /* emit compute-shader driver-params: */
+ uint32_t offset = v->constbase.driver_param;
+ if (v->constlen > offset) {
+ uint32_t compute_params[IR3_DP_CS_COUNT] = {
+ [IR3_DP_NUM_WORK_GROUPS_X] = info->grid[0],
+ [IR3_DP_NUM_WORK_GROUPS_Y] = info->grid[1],
+ [IR3_DP_NUM_WORK_GROUPS_Z] = info->grid[2],
+ /* do we need work-group-size? */
+ };
+
+ fd_wfi(ctx->batch, ring);
+ ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
+ ARRAY_SIZE(compute_params), compute_params, NULL);
+ }
+}
projects / mesa.git / blobdiff