freedreno/ir3: insert nop between sfu/mem operations

[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.h

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index fcd589534a2e9324bbc50819572b98f204d31fba..e5410bf88b292da228ef8c2a0f62207a95b14d21 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -69,14 +69,10 @@ struct ir3_shader_key {
                         */
                        unsigned color_two_side : 1;
                        unsigned half_precision : 1;
-                       /* For rendering to alpha, we need a bit of special handling
-                        * since the hw always takes gl_FragColor starting from x
-                        * component, rather than figuring out to take the w component.
-                        * We could be more clever and generate variants for other
-                        * render target formats (ie. luminance formats are xxx1), but
-                        * let's start with this and see how it goes:
+                       /* used when shader needs to handle flat varyings (a4xx),
+                        * for TGSI_INTERPOLATE_COLOR:
                         */
-                       unsigned alpha : 1;
+                       unsigned rasterflat : 1;
                };
                uint32_t global;
        };
@@ -137,7 +133,7 @@ struct ir3_shader_variant {
         * to bary.f instructions
         */
        uint8_t pos_regid;
-       bool frag_coord, frag_face;
+       bool frag_coord, frag_face, color0_mrt;
 
        /* varyings/outputs: */
        unsigned outputs_count;
@@ -182,6 +178,7 @@ struct ir3_shader_variant {
         * (not regid, because TGSI thinks in terms of vec4 registers,
         * not scalar registers)
         */
+       unsigned first_driver_param;
        unsigned first_immediate;
        unsigned immediates_count;
        struct {
@@ -210,6 +207,7 @@ struct ir3_shader {
        uint32_t vpsrepl[8];
 };
 
+void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 
 struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
                const struct tgsi_token *tokens, enum shader_t type);