freedreno/a4xx: better workaround for astc+srgb

[mesa.git] / src / gallium / drivers / freedreno / ir3 / ir3_shader.h

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 7e2c27d976517a4b0b2e7b9990d0620eff900863..e81e80d328f261fba66a0b1460104b63b33a5fbe 100644 (file)
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -30,7 +30,7 @@
 #define IR3_SHADER_H_
 
 #include "pipe/p_state.h"
-#include "glsl/nir/shader_enums.h"
+#include "compiler/shader_enums.h"
 
 #include "ir3.h"
 #include "disasm.h"
@@ -104,6 +104,9 @@ struct ir3_shader_key {
         * shader:
         */
        uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
+
+       /* bitmask of samplers which need astc srgb workaround: */
+       uint16_t vastc_srgb, fastc_srgb;
 };
 
 static inline bool
@@ -166,7 +169,9 @@ struct ir3_shader_variant {
        } outputs[16 + 2];  /* +POSITION +PSIZE */
        bool writes_pos, writes_psize;
 
-       /* vertices/inputs: */
+       /* attributes (VS) / varyings (FS):
+        * Note that sysval's should come *after* normal inputs.
+        */
        unsigned inputs_count;
        struct {
                uint8_t slot;
@@ -193,7 +198,15 @@ struct ir3_shader_variant {
                enum glsl_interp_qualifier interpolate;
        } inputs[16 + 2];  /* +POSITION +FACE */
 
-       unsigned total_in;       /* sum of inputs (scalar) */
+       /* sum of input components (scalar).  For frag shaders, it only counts
+        * the varying inputs:
+        */
+       unsigned total_in;
+
+       /* For frag shaders, the total number of inputs (not scalar,
+        * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
+        */
+       unsigned varying_in;
 
        /* do we have one or more texture sample instructions: */
        bool has_samp;
@@ -212,6 +225,14 @@ struct ir3_shader_variant {
                uint32_t val[4];
        } immediates[64];
 
+       /* for astc srgb workaround, the number/base of additional
+        * alpha tex states we need, and index of original tex states
+        */
+       struct {
+               unsigned base, count;
+               unsigned orig_idx[16];
+       } astc_srgb;
+
        /* shader variants form a linked list: */
        struct ir3_shader_variant *next;
 
@@ -220,6 +241,8 @@ struct ir3_shader_variant {
        struct ir3_shader *shader;
 };
 
+typedef struct nir_shader nir_shader;
+
 struct ir3_shader {
        enum shader_t type;
 
@@ -229,8 +252,7 @@ struct ir3_shader {
 
        struct ir3_compiler *compiler;
 
-       struct pipe_context *pctx;
-       const struct tgsi_token *tokens;
+       nir_shader *nir;
        struct pipe_stream_output_info stream_output;
 
        struct ir3_shader_variant *variants;
@@ -238,7 +260,7 @@ struct ir3_shader {
 
 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 
-struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
+struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
                const struct pipe_shader_state *cso, enum shader_t type);
 void ir3_shader_destroy(struct ir3_shader *shader);
 struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
@@ -246,8 +268,9 @@ struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
 
 struct fd_ringbuffer;
-void ir3_emit_consts(struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
-               const struct pipe_draw_info *info, uint32_t dirty);
+struct fd_context;
+void ir3_emit_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
+               struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t dirty);
 
 static inline const char *
 ir3_shader_stage(struct ir3_shader *shader)