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i915g: Use PIPE_FLUSH_END_OF_FRAME to trigger throttling
[mesa.git] / src / gallium / drivers / i915 / i915_clear.c
diff --git a/src/gallium/drivers/i915/i915_clear.c b/src/gallium/drivers/i915/i915_clear.c
index a0aba0201f5418fb17902d5048e9c481155cef1e..af75b8526af7d290a2e394803cb469cd1a788c8a 100644 (file)
--- a/src/gallium/drivers/i915/i915_clear.c
+++ b/src/gallium/drivers/i915/i915_clear.c
@@ -52,9 +52,11 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
    union util_color u_color;
    float f_depth = depth;
    struct i915_texture *cbuf_tex, *depth_tex;
+   int depth_clear_bbp, color_clear_bbp;
 
    cbuf_tex = depth_tex = NULL;
    clear_params = 0;
+   depth_clear_bbp = color_clear_bbp = 0;
 
    if (buffers & PIPE_CLEAR_COLOR) {
       struct pipe_surface *cbuf = i915->framebuffer.cbufs[0];
@@ -63,13 +65,16 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
       cbuf_tex = i915_texture(cbuf->texture);
 
       util_pack_color(color->f, cbuf->format, &u_color);
-      if (util_format_get_blocksize(cbuf_tex->b.b.format) == 4)
+      if (util_format_get_blocksize(cbuf_tex->b.b.format) == 4) {
          clear_color = u_color.ui;
-      else
+         color_clear_bbp = 32;
+      } else {
          clear_color = (u_color.ui & 0xffff) | (u_color.ui << 16);
+         color_clear_bbp = 16;
+      }
 
       /* correctly swizzle clear value */
-      if (i915->current.need_target_fixup)
+      if (i915->current.target_fixup_format)
          util_pack_color(color->f, cbuf->format, &u_color);
       else
          util_pack_color(color->f, PIPE_FORMAT_B8G8R8A8_UNORM, &u_color);
@@ -88,53 +93,120 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
       if (util_format_get_blocksize(depth_tex->b.b.format) == 4) {
          /* Avoid read-modify-write if there's no stencil. */
          if (buffers & PIPE_CLEAR_STENCIL
-               || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_USCALED) {
+               || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) {
             clear_params |= CLEARPARAM_WRITE_STENCIL;
-            clear_stencil = packed_z_stencil & 0xff;
-            clear_depth = packed_z_stencil;
-         } else
-            clear_depth = packed_z_stencil & 0xffffff00;
+            clear_stencil = packed_z_stencil >> 24;
+         }
+
+         clear_depth = packed_z_stencil & 0xffffff;
+         depth_clear_bbp = 32;
       } else {
-         clear_depth = (clear_depth & 0xffff) | (clear_depth << 16);
+         clear_depth = (packed_z_stencil & 0xffff) | (packed_z_stencil << 16);
+         depth_clear_bbp = 16;
       }
+   } else if (buffers & PIPE_CLEAR_STENCIL) {
+      struct pipe_surface *zbuf = i915->framebuffer.zsbuf;
+
+      clear_params |= CLEARPARAM_WRITE_STENCIL;
+      depth_tex = i915_texture(zbuf->texture);
+      assert(depth_tex->b.b.format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
+
+      packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil);
+      depth_clear_bbp = 32;
+      clear_stencil = packed_z_stencil >> 24;
    }
 
-   if (i915->hardware_dirty)
-      i915_emit_hardware_state(i915);
+   /* hw can't fastclear both depth and color if their bbp mismatch. */
+   if (color_clear_bbp && depth_clear_bbp
+         && color_clear_bbp != depth_clear_bbp) {
+      if (i915->hardware_dirty)
+         i915_emit_hardware_state(i915);
 
-   if (!BEGIN_BATCH(1 + 7 + 7)) {
-      FLUSH_BATCH(NULL);
+      if (!BEGIN_BATCH(1 + 2*(7 + 7))) {
+         FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
 
-      i915_emit_hardware_state(i915);
-      i915->vbo_flushed = 1;
+         i915_emit_hardware_state(i915);
+         i915->vbo_flushed = 1;
 
-      assert(BEGIN_BATCH(1 + 7 + 7));
-   }
+         assert(BEGIN_BATCH(1 + 2*(7 + 7)));
+      }
 
-   OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
-
-   OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
-   OUT_BATCH(clear_params | CLEARPARAM_CLEAR_RECT);
-   /* Used for zone init prim */
-   OUT_BATCH(clear_color);
-   OUT_BATCH(clear_depth);
-   /* Used for clear rect prim */
-   OUT_BATCH(clear_color8888);
-   OUT_BATCH_F(f_depth);
-   OUT_BATCH(clear_stencil);
-
-   OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
-   OUT_BATCH_F(destx + width);
-   OUT_BATCH_F(desty + height);
-   OUT_BATCH_F(destx);
-   OUT_BATCH_F(desty + height);
-   OUT_BATCH_F(destx);
-   OUT_BATCH_F(desty);
+      OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
+
+      OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
+      OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT);
+      /* Used for zone init prim */
+      OUT_BATCH(clear_color);
+      OUT_BATCH(clear_depth);
+      /* Used for clear rect prim */
+      OUT_BATCH(clear_color8888);
+      OUT_BATCH_F(f_depth);
+      OUT_BATCH(clear_stencil);
+
+      OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
+      OUT_BATCH_F(destx + width);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty);
+
+      OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
+      OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) |
+                CLEARPARAM_CLEAR_RECT);
+      /* Used for zone init prim */
+      OUT_BATCH(clear_color);
+      OUT_BATCH(clear_depth);
+      /* Used for clear rect prim */
+      OUT_BATCH(clear_color8888);
+      OUT_BATCH_F(f_depth);
+      OUT_BATCH(clear_stencil);
+
+      OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
+      OUT_BATCH_F(destx + width);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty);
+   } else {
+      if (i915->hardware_dirty)
+         i915_emit_hardware_state(i915);
+
+      if (!BEGIN_BATCH(1 + 7 + 7)) {
+         FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
+
+         i915_emit_hardware_state(i915);
+         i915->vbo_flushed = 1;
+
+         assert(BEGIN_BATCH(1 + 7 + 7));
+      }
+
+      OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
+
+      OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS);
+      OUT_BATCH(clear_params | CLEARPARAM_CLEAR_RECT);
+      /* Used for zone init prim */
+      OUT_BATCH(clear_color);
+      OUT_BATCH(clear_depth);
+      /* Used for clear rect prim */
+      OUT_BATCH(clear_color8888);
+      OUT_BATCH_F(f_depth);
+      OUT_BATCH(clear_stencil);
+
+      OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
+      OUT_BATCH_F(destx + width);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty + height);
+      OUT_BATCH_F(destx);
+      OUT_BATCH_F(desty);
+   }
 
    /* Flush after clear, its expected to be a costly operation.
     * This is not required, just a heuristic, but without the flush we'd need to
     * clobber the SCISSOR_ENABLE dynamic state. */
-   FLUSH_BATCH(NULL);
+   FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
 
    i915->last_fired_vertices = i915->fired_vertices;
    i915->fired_vertices = 0;