draw: inject frontface info into wireframe outputs

[mesa.git] / src / gallium / drivers / i915 / i915_clear.c

diff --git a/src/gallium/drivers/i915/i915_clear.c b/src/gallium/drivers/i915/i915_clear.c
index 8e2541d51d6e876e3b33c69ff8366e69a14f8e63..af75b8526af7d290a2e394803cb469cd1a788c8a 100644 (file)
--- a/src/gallium/drivers/i915/i915_clear.c
+++ b/src/gallium/drivers/i915/i915_clear.c
@@ -74,7 +74,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
       }
 
       /* correctly swizzle clear value */
-      if (i915->current.need_target_fixup)
+      if (i915->current.target_fixup_format)
          util_pack_color(color->f, cbuf->format, &u_color);
       else
          util_pack_color(color->f, PIPE_FORMAT_B8G8R8A8_UNORM, &u_color);
@@ -93,18 +93,27 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
       if (util_format_get_blocksize(depth_tex->b.b.format) == 4) {
          /* Avoid read-modify-write if there's no stencil. */
          if (buffers & PIPE_CLEAR_STENCIL
-               || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_USCALED) {
+               || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) {
             clear_params |= CLEARPARAM_WRITE_STENCIL;
-            clear_stencil = packed_z_stencil & 0xff;
-            clear_depth = packed_z_stencil;
-         } else
-            clear_depth = packed_z_stencil & 0xffffff00;
+            clear_stencil = packed_z_stencil >> 24;
+         }
 
+         clear_depth = packed_z_stencil & 0xffffff;
          depth_clear_bbp = 32;
       } else {
          clear_depth = (packed_z_stencil & 0xffff) | (packed_z_stencil << 16);
          depth_clear_bbp = 16;
       }
+   } else if (buffers & PIPE_CLEAR_STENCIL) {
+      struct pipe_surface *zbuf = i915->framebuffer.zsbuf;
+
+      clear_params |= CLEARPARAM_WRITE_STENCIL;
+      depth_tex = i915_texture(zbuf->texture);
+      assert(depth_tex->b.b.format == PIPE_FORMAT_Z24_UNORM_S8_UINT);
+
+      packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil);
+      depth_clear_bbp = 32;
+      clear_stencil = packed_z_stencil >> 24;
    }
 
    /* hw can't fastclear both depth and color if their bbp mismatch. */
@@ -114,7 +123,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
          i915_emit_hardware_state(i915);
 
       if (!BEGIN_BATCH(1 + 2*(7 + 7))) {
-         FLUSH_BATCH(NULL);
+         FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
 
          i915_emit_hardware_state(i915);
          i915->vbo_flushed = 1;
@@ -146,7 +155,6 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
       OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) |
                 CLEARPARAM_CLEAR_RECT);
       /* Used for zone init prim */
-      /* Used for zone init prim */
       OUT_BATCH(clear_color);
       OUT_BATCH(clear_depth);
       /* Used for clear rect prim */
@@ -166,7 +174,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
          i915_emit_hardware_state(i915);
 
       if (!BEGIN_BATCH(1 + 7 + 7)) {
-         FLUSH_BATCH(NULL);
+         FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
 
          i915_emit_hardware_state(i915);
          i915->vbo_flushed = 1;
@@ -198,7 +206,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers,
    /* Flush after clear, its expected to be a costly operation.
     * This is not required, just a heuristic, but without the flush we'd need to
     * clobber the SCISSOR_ENABLE dynamic state. */
-   FLUSH_BATCH(NULL);
+   FLUSH_BATCH(NULL, I915_FLUSH_ASYNC);
 
    i915->last_fired_vertices = i915->fired_vertices;
    i915->fired_vertices = 0;