r600g: Move fetch shader register setup to r600_state.c / evergreen_state.c.

[mesa.git] / src / gallium / drivers / i915 / i915_state_static.c

diff --git a/src/gallium/drivers/i915/i915_state_static.c b/src/gallium/drivers/i915/i915_state_static.c
index 20cd23f8f736cf833d5fced426f4763028d856cc..70b3dffee3ddde0acdc11f2f636a7356f564063b 100644 (file)
--- a/src/gallium/drivers/i915/i915_state_static.c
+++ b/src/gallium/drivers/i915/i915_state_static.c
@@ -78,29 +78,6 @@ buf_3d_tiling_bits(enum i915_winsys_buffer_tile tiling)
    return tiling_bits;
 }
 
-/**
- * Examine framebuffer state to determine width, height.
- */
-static boolean
-framebuffer_size(const struct pipe_framebuffer_state *fb,
-                 uint *width, uint *height)
-{
-   if (fb->cbufs[0]) {
-      *width = fb->cbufs[0]->width;
-      *height = fb->cbufs[0]->height;
-      return TRUE;
-   }
-   else if (fb->zsbuf) {
-      *width = fb->zsbuf->width;
-      *height = fb->zsbuf->height;
-      return TRUE;
-   }
-   else {
-      *width = *height = 0;
-      return FALSE;
-   }
-}
-
 static void update_framebuffer(struct i915_context *i915)
 {
    struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
@@ -109,7 +86,6 @@ static void update_framebuffer(struct i915_context *i915)
    unsigned x, y, w, h;
    int layer;
    uint32_t draw_offset;
-   boolean ret;
 
    if (cbuf_surface) {
       struct i915_texture *tex = i915_texture(cbuf_surface->texture);
@@ -160,12 +136,13 @@ static void update_framebuffer(struct i915_context *i915)
 
    /* drawing rect calculations */
    draw_offset = x | (y << 16);
-   ret = framebuffer_size(&i915->framebuffer, &w, &h);
-   assert(ret);
    if (i915->current.draw_offset != draw_offset) {
       i915->current.draw_offset = draw_offset;
       i915_set_flush_dirty(i915, I915_PIPELINE_FLUSH);
    }
+
+   w = i915->framebuffer.width;
+   h = i915->framebuffer.height;
    i915->current.draw_size = (w - 1 + x) | ((h - 1 + y) << 16);
 
    i915->hardware_dirty |= I915_HW_STATIC;