gallium: separate out floating-point CAPs into its own enum

[mesa.git] / src / gallium / drivers / i965 / brw_screen.c

diff --git a/src/gallium/drivers/i965/brw_screen.c b/src/gallium/drivers/i965/brw_screen.c
index 864b21fa53c3cab0cdee1c41c3fea240ef3f0c47..b382e703a0c182d2d7fbcc3befef00547cbaa9d6 100644 (file)
--- a/src/gallium/drivers/i965/brw_screen.c
+++ b/src/gallium/drivers/i965/brw_screen.c
@@ -26,6 +26,7 @@
  **************************************************************************/
 
 
+#include "util/u_format.h"
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
 #include "util/u_string.h"
@@ -97,7 +98,7 @@ brw_get_name(struct pipe_screen *screen)
    static char buffer[128];
    const char *chipset;
 
-   switch (brw_screen(screen)->chipset.pci_id) {
+   switch (brw_screen(screen)->pci_id) {
    case PCI_CHIP_I965_G:
       chipset = "I965_G";
       break;
@@ -153,18 +154,12 @@ static int
 brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
 {
    switch (param) {
-   case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
-      return 8;
-   case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
-      return 8;
    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
       return 16; /* XXX correct? */
    case PIPE_CAP_NPOT_TEXTURES:
       return 1;
    case PIPE_CAP_TWO_SIDED_STENCIL:
       return 1;
-   case PIPE_CAP_GLSL:
-      return 0;
    case PIPE_CAP_ANISOTROPIC_FILTER:
       return 0;
    case PIPE_CAP_POINT_SPRITE:
@@ -235,6 +230,17 @@ brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shad
          return 0;
       case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
          return 1;
+      case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
+      case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
+      case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
+      case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
+          return 1;
+      case PIPE_SHADER_CAP_SUBROUTINES:
+          return 1;
+      case PIPE_SHADER_CAP_INTEGERS:
+         return 0;
+      case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
+         return 8;
       default:
          assert(0);
          return 0;
@@ -242,23 +248,23 @@ brw_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shad
 }
 
 static float
-brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
+brw_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 {
    switch (param) {
-   case PIPE_CAP_MAX_LINE_WIDTH:
+   case PIPE_CAPF_MAX_LINE_WIDTH:
       /* fall-through */
-   case PIPE_CAP_MAX_LINE_WIDTH_AA:
+   case PIPE_CAPF_MAX_LINE_WIDTH_AA:
       return 7.5;
 
-   case PIPE_CAP_MAX_POINT_WIDTH:
+   case PIPE_CAPF_MAX_POINT_WIDTH:
       /* fall-through */
-   case PIPE_CAP_MAX_POINT_WIDTH_AA:
+   case PIPE_CAPF_MAX_POINT_WIDTH_AA:
       return 255.0;
 
-   case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+   case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
       return 4.0;
 
-   case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+   case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
       return 16.0;
 
    default:
@@ -271,8 +277,7 @@ brw_is_format_supported(struct pipe_screen *screen,
                          enum pipe_format format,
                          enum pipe_texture_target target,
                          unsigned sample_count,
-                         unsigned tex_usage,
-                         unsigned geom_flags)
+                         unsigned tex_usage)
 {
    static const enum pipe_format tex_supported[] = {
       PIPE_FORMAT_L8_UNORM,
@@ -304,7 +309,7 @@ brw_is_format_supported(struct pipe_screen *screen,
       /* depth */
       PIPE_FORMAT_Z32_FLOAT,
       PIPE_FORMAT_Z24X8_UNORM,
-      PIPE_FORMAT_Z24_UNORM_S8_USCALED,
+      PIPE_FORMAT_Z24_UNORM_S8_UINT,
       PIPE_FORMAT_Z16_UNORM,
       /* signed */
       PIPE_FORMAT_R8G8_SNORM,
@@ -320,13 +325,16 @@ brw_is_format_supported(struct pipe_screen *screen,
    static const enum pipe_format depth_supported[] = {
       PIPE_FORMAT_Z32_FLOAT,
       PIPE_FORMAT_Z24X8_UNORM,
-      PIPE_FORMAT_Z24_UNORM_S8_USCALED,
+      PIPE_FORMAT_Z24_UNORM_S8_UINT,
       PIPE_FORMAT_Z16_UNORM,
       PIPE_FORMAT_NONE  /* list terminator */
    };
    const enum pipe_format *list;
    uint i;
 
+   if (!util_format_is_supported(format, tex_usage))
+      return FALSE;
+
    if (sample_count > 1)
       return FALSE;
 
@@ -358,20 +366,19 @@ brw_fence_reference(struct pipe_screen *screen,
 {
 }
 
-static int
+static boolean
 brw_fence_signalled(struct pipe_screen *screen,
-                     struct pipe_fence_handle *fence,
-                     unsigned flags)
+                     struct pipe_fence_handle *fence)
 {
-   return 0;                    /* XXX shouldn't this be a boolean? */
+   return TRUE;
 }
 
-static int
+static boolean
 brw_fence_finish(struct pipe_screen *screen,
                  struct pipe_fence_handle *fence,
-                 unsigned flags)
+                 uint64_t timeout)
 {
-   return 0;
+   return TRUE;
 }
 
 
@@ -398,8 +405,6 @@ struct pipe_screen *
 brw_screen_create(struct brw_winsys_screen *sws)
 {
    struct brw_screen *bscreen;
-   struct brw_chipset chipset;
-
 #ifdef DEBUG
    BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
    BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
@@ -408,46 +413,30 @@ brw_screen_create(struct brw_winsys_screen *sws)
    BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
 #endif
 
-   memset(&chipset, 0, sizeof chipset);
-
-   chipset.pci_id = sws->pci_id;
-
-   switch (chipset.pci_id) {
-   case PCI_CHIP_I965_G:
-   case PCI_CHIP_I965_Q:
-   case PCI_CHIP_I965_G_1:
-   case PCI_CHIP_I946_GZ:
-   case PCI_CHIP_I965_GM:
-   case PCI_CHIP_I965_GME:
-      chipset.is_965 = TRUE;
-      break;
-
-   case PCI_CHIP_GM45_GM:
-   case PCI_CHIP_IGD_E_G:
-   case PCI_CHIP_Q45_G:
-   case PCI_CHIP_G45_G:
-   case PCI_CHIP_G41_G:
-   case PCI_CHIP_B43_G:
-      chipset.is_g4x = TRUE;
-      break;
-
-   case PCI_CHIP_ILD_G:
-   case PCI_CHIP_ILM_G:
-      chipset.is_igdng = TRUE;
-      break;
+   bscreen = CALLOC_STRUCT(brw_screen);
+   if (!bscreen)
+      return NULL;
 
-   default:
+   bscreen->pci_id = sws->pci_id;
+   if (IS_GEN6(sws->pci_id)) {
+       bscreen->gen = 6;
+       bscreen->needs_ff_sync = TRUE;
+   } else if (IS_GEN5(sws->pci_id)) {
+       bscreen->gen = 5;
+       bscreen->needs_ff_sync = TRUE;
+   } else if (IS_965(sws->pci_id)) {
+       bscreen->gen = 4;
+       if (IS_G4X(sws->pci_id)) {
+          bscreen->is_g4x = true;
+       }
+   } else {
       debug_printf("%s: unknown pci id 0x%x, cannot create screen\n", 
-                   __FUNCTION__, chipset.pci_id);
+                   __FUNCTION__, sws->pci_id);
+      free(bscreen);
       return NULL;
    }
 
-
-   bscreen = CALLOC_STRUCT(brw_screen);
-   if (!bscreen)
-      return NULL;
-
-   bscreen->chipset = chipset;
+   sws->gen = bscreen->gen;
    bscreen->sws = sws;
    bscreen->base.winsys = NULL;
    bscreen->base.destroy = brw_destroy_screen;
@@ -463,7 +452,6 @@ brw_screen_create(struct brw_winsys_screen *sws)
    bscreen->base.fence_finish = brw_fence_finish;
 
    brw_init_screen_resource_functions(bscreen);
-   brw_screen_tex_surface_init(bscreen);
 
    bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;