**************************************************************************/
-#include "pipe/p_inlines.h"
+#include "util/u_inlines.h"
#include "util/u_memory.h"
#include "util/u_string.h"
#include "brw_context.h"
#include "brw_screen.h"
#include "brw_winsys.h"
+#include "brw_public.h"
#include "brw_debug.h"
+#include "brw_resource.h"
#ifdef DEBUG
static const struct debug_named_value debug_names[] = {
- { "tex", DEBUG_TEXTURE},
- { "state", DEBUG_STATE},
- { "ioctl", DEBUG_IOCTL},
- { "blit", DEBUG_BLIT},
- { "curbe", DEBUG_CURBE},
- { "fall", DEBUG_FALLBACKS},
- { "verb", DEBUG_VERBOSE},
- { "bat", DEBUG_BATCH},
- { "pix", DEBUG_PIXEL},
- { "buf", DEBUG_BUFMGR},
- { "sync", DEBUG_SYNC},
- { "prim", DEBUG_PRIMS },
- { "vert", DEBUG_VERTS },
- { "dma", DEBUG_DMA },
- { "san", DEBUG_SANITY },
- { "sleep", DEBUG_SLEEP },
- { "stats", DEBUG_STATS },
- { "sing", DEBUG_SINGLE_THREAD },
- { "thre", DEBUG_SINGLE_THREAD },
- { "wm", DEBUG_WM },
- { "urb", DEBUG_URB },
- { "vs", DEBUG_VS },
- { NULL, 0 }
+ { "tex", DEBUG_TEXTURE, NULL },
+ { "state", DEBUG_STATE, NULL },
+ { "ioctl", DEBUG_IOCTL, NULL },
+ { "blit", DEBUG_BLIT, NULL },
+ { "curbe", DEBUG_CURBE, NULL },
+ { "fall", DEBUG_FALLBACKS, NULL },
+ { "verb", DEBUG_VERBOSE, NULL },
+ { "bat", DEBUG_BATCH, NULL },
+ { "pix", DEBUG_PIXEL, NULL },
+ { "wins", DEBUG_WINSYS, NULL },
+ { "min", DEBUG_MIN_URB, NULL },
+ { "dis", DEBUG_DISASSEM, NULL },
+ { "sync", DEBUG_SYNC, NULL },
+ { "prim", DEBUG_PRIMS, NULL },
+ { "vert", DEBUG_VERTS, NULL },
+ { "dma", DEBUG_DMA, NULL },
+ { "san", DEBUG_SANITY, NULL },
+ { "sleep", DEBUG_SLEEP, NULL },
+ { "stats", DEBUG_STATS, NULL },
+ { "sing", DEBUG_SINGLE_THREAD, NULL },
+ { "thre", DEBUG_SINGLE_THREAD, NULL },
+ { "wm", DEBUG_WM, NULL },
+ { "urb", DEBUG_URB, NULL },
+ { "vs", DEBUG_VS, NULL },
+ DEBUG_NAMED_VALUE_END
+};
+
+static const struct debug_named_value dump_names[] = {
+ { "asm", DUMP_ASM, NULL },
+ { "state", DUMP_STATE, NULL },
+ { "batch", DUMP_BATCH, NULL },
+ DEBUG_NAMED_VALUE_END
};
int BRW_DEBUG = 0;
+int BRW_DUMP = 0;
+
#endif
case PCI_CHIP_ILM_G:
chipset = "ILM_G";
break;
+ default:
+ chipset = "unknown";
+ break;
}
util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
}
static int
-brw_get_param(struct pipe_screen *screen, int param)
+brw_get_param(struct pipe_screen *screen, enum pipe_cap param)
{
switch (param) {
case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
return 8;
+ case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
+ return 8;
+ case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+ return 16; /* XXX correct? */
case PIPE_CAP_NPOT_TEXTURES:
return 1;
case PIPE_CAP_TWO_SIDED_STENCIL:
return 1;
case PIPE_CAP_OCCLUSION_QUERY:
return 0;
+ case PIPE_CAP_TIMER_QUERY:
+ return 0;
case PIPE_CAP_TEXTURE_SHADOW_MAP:
return 1;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
- return 11; /* max 1024x1024 */
+ return BRW_MAX_TEXTURE_2D_LEVELS;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- return 8; /* max 128x128x128 */
+ return BRW_MAX_TEXTURE_3D_LEVELS;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 11; /* max 1024x1024 */
+ return BRW_MAX_TEXTURE_2D_LEVELS;
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+ return 1;
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+ return 0;
+ case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+ /* disable for now */
+ return 0;
default:
return 0;
}
}
static float
-brw_get_paramf(struct pipe_screen *screen, int param)
+brw_get_paramf(struct pipe_screen *screen, enum pipe_cap param)
{
switch (param) {
case PIPE_CAP_MAX_LINE_WIDTH:
static boolean
brw_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
+ enum pipe_format format,
enum pipe_texture_target target,
- unsigned tex_usage,
+ unsigned sample_count,
+ unsigned tex_usage,
unsigned geom_flags)
{
static const enum pipe_format tex_supported[] = {
- PIPE_FORMAT_R8G8B8A8_UNORM,
- PIPE_FORMAT_A8R8G8B8_UNORM,
- PIPE_FORMAT_R5G6B5_UNORM,
PIPE_FORMAT_L8_UNORM,
- PIPE_FORMAT_A8_UNORM,
PIPE_FORMAT_I8_UNORM,
- PIPE_FORMAT_A8L8_UNORM,
- PIPE_FORMAT_YCBCR,
- PIPE_FORMAT_YCBCR_REV,
- PIPE_FORMAT_S8Z24_UNORM,
+ PIPE_FORMAT_A8_UNORM,
+ PIPE_FORMAT_L16_UNORM,
+ /*PIPE_FORMAT_I16_UNORM,*/
+ /*PIPE_FORMAT_A16_UNORM,*/
+ PIPE_FORMAT_L8A8_UNORM,
+ PIPE_FORMAT_B5G6R5_UNORM,
+ PIPE_FORMAT_B5G5R5A1_UNORM,
+ PIPE_FORMAT_B4G4R4A4_UNORM,
+ PIPE_FORMAT_B8G8R8X8_UNORM,
+ PIPE_FORMAT_B8G8R8A8_UNORM,
+ /* video */
+ PIPE_FORMAT_UYVY,
+ PIPE_FORMAT_YUYV,
+ /* compressed */
+ /*PIPE_FORMAT_FXT1_RGBA,*/
+ PIPE_FORMAT_DXT1_RGB,
+ PIPE_FORMAT_DXT1_RGBA,
+ PIPE_FORMAT_DXT3_RGBA,
+ PIPE_FORMAT_DXT5_RGBA,
+ /* sRGB */
+ PIPE_FORMAT_A8B8G8R8_SRGB,
+ PIPE_FORMAT_L8A8_SRGB,
+ PIPE_FORMAT_L8_SRGB,
+ PIPE_FORMAT_DXT1_SRGB,
+ /* depth */
+ PIPE_FORMAT_Z32_FLOAT,
+ PIPE_FORMAT_Z24X8_UNORM,
+ PIPE_FORMAT_Z24_UNORM_S8_USCALED,
+ PIPE_FORMAT_Z16_UNORM,
+ /* signed */
+ PIPE_FORMAT_R8G8_SNORM,
+ PIPE_FORMAT_R8G8B8A8_SNORM,
PIPE_FORMAT_NONE /* list terminator */
};
- static const enum pipe_format surface_supported[] = {
- PIPE_FORMAT_A8R8G8B8_UNORM,
- PIPE_FORMAT_R5G6B5_UNORM,
- PIPE_FORMAT_S8Z24_UNORM,
+ static const enum pipe_format render_supported[] = {
+ PIPE_FORMAT_B8G8R8X8_UNORM,
+ PIPE_FORMAT_B8G8R8A8_UNORM,
+ PIPE_FORMAT_B5G6R5_UNORM,
+ PIPE_FORMAT_NONE /* list terminator */
+ };
+ static const enum pipe_format depth_supported[] = {
+ PIPE_FORMAT_Z32_FLOAT,
+ PIPE_FORMAT_Z24X8_UNORM,
+ PIPE_FORMAT_Z24_UNORM_S8_USCALED,
+ PIPE_FORMAT_Z16_UNORM,
PIPE_FORMAT_NONE /* list terminator */
};
const enum pipe_format *list;
uint i;
- if(tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
- list = surface_supported;
+ if (sample_count > 1)
+ return FALSE;
+
+ if (tex_usage & PIPE_BIND_DEPTH_STENCIL)
+ list = depth_supported;
+ else if (tex_usage & PIPE_BIND_RENDER_TARGET)
+ list = render_supported;
else
list = tex_supported;
* Create a new brw_screen object
*/
struct pipe_screen *
-brw_create_screen(struct brw_winsys_screen *sws, uint pci_id)
+brw_screen_create(struct brw_winsys_screen *sws)
{
struct brw_screen *bscreen;
struct brw_chipset chipset;
#ifdef DEBUG
BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
+ BRW_DEBUG |= DEBUG_STATS | DEBUG_MIN_URB | DEBUG_WM;
+
+ BRW_DUMP = debug_get_flags_option("BRW_DUMP", dump_names, 0);
#endif
memset(&chipset, 0, sizeof chipset);
- chipset.pci_id = pci_id;
+ chipset.pci_id = sws->pci_id;
- switch (pci_id) {
+ switch (chipset.pci_id) {
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I965_G_1:
default:
debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
- __FUNCTION__, pci_id);
+ __FUNCTION__, chipset.pci_id);
return NULL;
}
bscreen->base.get_param = brw_get_param;
bscreen->base.get_paramf = brw_get_paramf;
bscreen->base.is_format_supported = brw_is_format_supported;
+ bscreen->base.context_create = brw_create_context;
bscreen->base.fence_reference = brw_fence_reference;
bscreen->base.fence_signalled = brw_fence_signalled;
bscreen->base.fence_finish = brw_fence_finish;
- brw_screen_tex_init(bscreen);
+ brw_init_screen_resource_functions(bscreen);
brw_screen_tex_surface_init(bscreen);
- brw_screen_init_buffer_functions(bscreen);
+ bscreen->no_tiling = debug_get_option("BRW_NO_TILING", FALSE) != NULL;
+
+
return &bscreen->base;
}