Merge branch '7.8'

[mesa.git] / src / gallium / drivers / i965 / brw_structs.h

diff --git a/src/gallium/drivers/i965/brw_structs.h b/src/gallium/drivers/i965/brw_structs.h
index 66d4127271afced963587ad21919ee639f496c0c..e97ddeb5e1cf729759b39afccc7e71c2e817b55a 100644 (file)
--- a/src/gallium/drivers/i965/brw_structs.h
+++ b/src/gallium/drivers/i965/brw_structs.h
@@ -28,11 +28,12 @@
   * Authors:
   *   Keith Whitwell <keith@tungstengraphics.com>
   */
-        
+
 
 #ifndef BRW_STRUCTS_H
 #define BRW_STRUCTS_H
 
+#include "brw_types.h"
 
 /** Number of general purpose registers (VS, WM, etc) */
 #define BRW_MAX_GRF 128
@@ -662,7 +663,7 @@ struct brw_clip_unit_state
 
 struct brw_cc_unit_state
 {
-   struct
+   struct brw_cc0
    {
       GLuint pad0:3;
       GLuint bf_stencil_pass_depth_pass_op:3; 
@@ -680,7 +681,7 @@ struct brw_cc_unit_state
    } cc0;
 
    
-   struct
+   struct brw_cc1
    {
       GLuint bf_stencil_ref:8; 
       GLuint stencil_write_mask:8; 
@@ -689,7 +690,7 @@ struct brw_cc_unit_state
    } cc1;
 
    
-   struct
+   struct brw_cc2
    {
       GLuint logicop_enable:1; 
       GLuint pad0:10;
@@ -701,7 +702,7 @@ struct brw_cc_unit_state
    } cc2;
 
    
-   struct
+   struct brw_cc3
    {
       GLuint pad0:8;
       GLuint alpha_test_func:3; 
@@ -713,13 +714,13 @@ struct brw_cc_unit_state
       GLuint pad2:16;
    } cc3;
    
-   struct
+   struct brw_cc4
    {
       GLuint pad0:5; 
       GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */
    } cc4;
    
-   struct
+   struct brw_cc5
    {
       GLuint pad0:2;
       GLuint ia_dest_blend_factor:5; 
@@ -731,7 +732,7 @@ struct brw_cc_unit_state
       GLuint dither_enable:1; 
    } cc5;
 
-   struct
+   struct brw_cc6
    {
       GLuint clamp_post_alpha_blend:1; 
       GLuint clamp_pre_alpha_blend:1; 
@@ -744,7 +745,7 @@ struct brw_cc_unit_state
       GLuint blend_function:3; 
    } cc6;
 
-   struct {
+   struct brw_cc7 {
       union {
         GLfloat f;  
         GLubyte ub[4];
@@ -964,7 +965,7 @@ struct brw_sampler_default_color {
 struct brw_sampler_state
 {
    
-   struct
+   struct brw_ss0
    {
       GLuint shadow_function:3; 
       GLuint lod_bias:11; 
@@ -979,7 +980,7 @@ struct brw_sampler_state
       GLuint disable:1; 
    } ss0;
 
-   struct
+   struct brw_ss1
    {
       GLuint r_wrap_mode:3; 
       GLuint t_wrap_mode:3; 
@@ -990,13 +991,13 @@ struct brw_sampler_state
    } ss1;
 
    
-   struct
+   struct brw_ss2
    {
       GLuint pad:5;
       GLuint default_color_pointer:27; 
    } ss2;
    
-   struct
+   struct brw_ss3
    {
       GLuint pad:19;
       GLuint max_aniso:3; 
@@ -1047,7 +1048,7 @@ struct brw_sf_viewport
  */
 struct brw_surface_state
 {
-   struct {
+   struct brw_surf_ss0 {
       GLuint cube_pos_z:1; 
       GLuint cube_neg_z:1; 
       GLuint cube_pos_y:1; 
@@ -1069,18 +1070,18 @@ struct brw_surface_state
       GLuint surface_type:3;       /**< BRW_SURFACE_1D/2D/3D/CUBE */
    } ss0;
    
-   struct {
+   struct brw_surf_ss1 {
       GLuint base_addr;  
    } ss1;
    
-   struct {
+   struct brw_surf_ss2 {
       GLuint pad:2;
       GLuint mip_count:4; 
       GLuint width:13; 
       GLuint height:13; 
    } ss2;
 
-   struct {
+   struct brw_surf_ss3 {
       GLuint tile_walk:1; 
       GLuint tiled_surface:1; 
       GLuint pad:1; 
@@ -1088,7 +1089,7 @@ struct brw_surface_state
       GLuint depth:11; 
    } ss3;
    
-   struct {
+   struct brw_surf_ss4 {
       GLuint multisample_position_palette_index:3;
       GLuint pad1:1;
       GLuint num_multisamples:3;
@@ -1098,7 +1099,7 @@ struct brw_surface_state
       GLuint min_lod:4; 
    } ss4;
 
-   struct {
+   struct brw_surf_ss5 {
       GLuint pad1:16;
       GLuint llc_mapping:1;
       GLuint mlc_mapping:1;
@@ -1148,7 +1149,7 @@ struct brw_vertex_element_state
       GLuint valid:1; 
       GLuint vertex_buffer_index:5; 
    } ve0;
-   
+
    struct
    {
       GLuint dst_offset:8;