#include "brw_context.h"
#include "brw_vs.h"
#include "brw_debug.h"
+#include "brw_disasm.h"
/* Choose one of the 4 vec4's which can be packed into each 16-wide reg.
*/
static boolean is_position_output( struct brw_vs_compile *c,
unsigned vs_output )
{
- struct brw_vertex_shader *vs = c->vp;
-
- if (vs_output == c->prog_data.output_edgeflag) {
- return FALSE;
- }
- else {
- unsigned semantic = vs->info.output_semantic_name[vs_output];
- unsigned index = vs->info.output_semantic_index[vs_output];
+ const struct brw_vertex_shader *vs = c->vp;
+ unsigned semantic = vs->info.output_semantic_name[vs_output];
+ unsigned index = vs->info.output_semantic_index[vs_output];
- return (semantic == TGSI_SEMANTIC_POSITION &&
- index == 0);
- }
+ return (semantic == TGSI_SEMANTIC_POSITION &&
+ index == 0);
}
unsigned vs_output,
unsigned *fs_input_slot )
{
- struct brw_vertex_shader *vs = c->vp;
-
- if (vs_output == c->prog_data.output_edgeflag) {
- *fs_input_slot = c->key.fs_signature.nr_inputs;
- return TRUE;
- }
- else {
- unsigned semantic = vs->info.output_semantic_name[vs_output];
- unsigned index = vs->info.output_semantic_index[vs_output];
- unsigned i;
+ const struct brw_vertex_shader *vs = c->vp;
+ unsigned semantic = vs->info.output_semantic_name[vs_output];
+ unsigned index = vs->info.output_semantic_index[vs_output];
+ unsigned i;
- for (i = 0; i < c->key.fs_signature.nr_inputs; i++) {
- if (c->key.fs_signature.input[i].semantic == semantic &&
+ for (i = 0; i < c->key.fs_signature.nr_inputs; i++) {
+ if (c->key.fs_signature.input[i].semantic == semantic &&
c->key.fs_signature.input[i].semantic_index == index) {
- *fs_input_slot = i;
- return TRUE;
- }
+ *fs_input_slot = i;
+ return TRUE;
}
}
}
+#if 0
/* TODO: relative addressing!
*/
}
}
+#endif
+
/**
* Indirect addressing: get reg[[arg] + offset].
{
struct brw_reg reg;
- if (src->SrcRegister.File == TGSI_FILE_NULL)
+ if (src->Register.File == TGSI_FILE_NULL)
return brw_null_reg();
reg = get_src_reg(c, argIndex,
- src->SrcRegister.File,
- src->SrcRegister.Index,
- src->SrcRegister.Indirect);
+ src->Register.File,
+ src->Register.Index,
+ src->Register.Indirect);
/* Convert 3-bit swizzle to 2-bit.
*/
- reg.dw1.bits.swizzle = BRW_SWIZZLE4(src->SrcRegister.SwizzleX,
- src->SrcRegister.SwizzleY,
- src->SrcRegister.SwizzleZ,
- src->SrcRegister.SwizzleW);
+ reg.dw1.bits.swizzle = BRW_SWIZZLE4(src->Register.SwizzleX,
+ src->Register.SwizzleY,
+ src->Register.SwizzleZ,
+ src->Register.SwizzleW);
- reg.negate = src->SrcRegister.Negate ? 1 : 0;
+ reg.negate = src->Register.Negate ? 1 : 0;
/* XXX: abs, absneg
*/
int i;
GLuint len_vertext_header = 2;
- if (c->key.copy_edgeflag) {
- brw_MOV(p,
- get_reg(c, TGSI_FILE_OUTPUT, c->prog_data.output_edgeflag),
- brw_imm_f(1));
- }
-
/* Build ndc coords */
ndc = get_tmp(c);
/* ndc = 1.0 / pos.w */
const struct tgsi_full_instruction *inst)
{
unsigned opcode = inst->Instruction.Opcode;
- unsigned label = inst->InstructionExtLabel.Label;
+ unsigned label = inst->Label.Label;
struct brw_compile *p = &c->func;
struct brw_reg args[3], dst;
GLuint i;
/* Get argument regs.
*/
for (i = 0; i < 3; i++) {
- args[i] = get_arg(c, &inst->FullSrcRegisters[i], i);
+ args[i] = get_arg(c, &inst->Src[i], i);
}
/* Get dest regs. Note that it is possible for a reg to be both
* care needs to be taken emitting multi-operation instructions.
*/
dst = get_dst(c,
- inst->FullDstRegisters[0].DstRegister.File,
- inst->FullDstRegisters[0].DstRegister.Index,
- inst->FullDstRegisters[0].DstRegister.WriteMask);
+ inst->Dst[0].Register.File,
+ inst->Dst[0].Register.Index,
+ inst->Dst[0].Register.WriteMask);
/* XXX: saturate
*/
emit_math1(c, BRW_MATH_FUNCTION_INV, dst, args[0], BRW_MATH_PRECISION_FULL);
break;
case TGSI_OPCODE_RSQ:
- emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, args[0], BRW_MATH_PRECISION_FULL);
+ emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst,
+ brw_swizzle(args[0], 0,0,0,0), BRW_MATH_PRECISION_FULL);
break;
case TGSI_OPCODE_SEQ:
emit_seq(p, dst, args[0], args[1]);