gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
bool caller_post_sync)
{
- assert(p->gen == ILO_GEN(6));
+ assert(p->dev->gen == ILO_GEN(6));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
*
* The workaround below necessitates this workaround.
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
* "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
* PIPE_CONTROL with any non-zero post-sync-op is required."
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_WRITE_IMMEDIATE,
p->workaround_bo, 0, false, p->cp);
}
static void
gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
{
- assert(p->gen == ILO_GEN(6));
+ assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
* requires driver to send a PIPE_CONTROL with a CS stall along with a
* Depth Flush prior to this command."
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
PIPE_CONTROL_CS_STALL,
0, 0, false, p->cp);
static void
gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
{
- assert(p->gen == ILO_GEN(6));
+ assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
* to emit a sequence of PIPE_CONTROLs prior to emitting depth related
* commands.
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH,
NULL, 0, false, p->cp);
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
}
static void
gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
{
- assert(p->gen == ILO_GEN(6));
+ assert(p->dev->gen == ILO_GEN(6));
/* the post-sync workaround should cover this already */
if (p->state.has_gen6_wa_pipe_control)
* field set (DW1 Bit 1), must be issued prior to any change to the
* value in this field (Maximum Number of Threads in 3DSTATE_WM)"
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
static void
gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
{
- assert(p->gen == ILO_GEN(6));
+ assert(p->dev->gen == ILO_GEN(6));
gen6_wa_pipe_control_post_sync(p, false);
* PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
* buffered by VS FF, to the point that the FF dies.
*/
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_STATE_CACHE_INVALIDATE,
{
/* PIPELINE_SELECT */
if (session->hw_ctx_changed) {
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_PIPELINE_SELECT(&p->gpe, 0x0, p->cp);
+ p->gen6_PIPELINE_SELECT(p->dev, 0x0, p->cp);
}
}
{
/* STATE_SIP */
if (session->hw_ctx_changed) {
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_STATE_SIP(&p->gpe, 0, p->cp);
+ p->gen6_STATE_SIP(p->dev, 0, p->cp);
}
}
struct gen6_pipeline_session *session)
{
/* STATE_BASE_ADDRESS */
- if (session->state_bo_changed || session->instruction_bo_changed) {
- if (p->gen == ILO_GEN(6))
+ if (session->state_bo_changed || session->instruction_bo_changed ||
+ session->batch_bo_changed) {
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_STATE_BASE_ADDRESS(&p->gpe,
+ p->gen6_STATE_BASE_ADDRESS(p->dev,
NULL, p->cp->bo, p->cp->bo, NULL, ilo->shader_cache->bo,
0, 0, 0, 0, p->cp);
* VS-generated output data, output URB availability isn't a
* factor."
*/
- if (vs_entry_size < ilo->vertex_elements->num_elements)
- vs_entry_size = ilo->vertex_elements->num_elements;
+ if (vs_entry_size < ilo->ve->count)
+ vs_entry_size = ilo->ve->count;
gs_entry_size = (gs) ? gs->out.count :
(vs && vs->stream_output) ? vs_entry_size : 0;
/* in bytes */
vs_entry_size *= sizeof(float) * 4;
gs_entry_size *= sizeof(float) * 4;
- vs_total_size = ilo->urb.size * 1024;
+ vs_total_size = ilo->dev->urb_size;
if (gs_active) {
vs_total_size /= 2;
gs_total_size = 0;
}
- p->gen6_3DSTATE_URB(&p->gpe, vs_total_size, gs_total_size,
+ p->gen6_3DSTATE_URB(p->dev, vs_total_size, gs_total_size,
vs_entry_size, gs_entry_size, p->cp);
/*
{
/* 3DSTATE_VIEWPORT_STATE_POINTERS */
if (session->viewport_state_changed) {
- p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(&p->gpe,
+ p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->dev,
p->state.CLIP_VIEWPORT,
p->state.SF_VIEWPORT,
p->state.CC_VIEWPORT, p->cp);
if (session->cc_state_blend_changed ||
session->cc_state_dsa_changed ||
session->cc_state_cc_changed) {
- p->gen6_3DSTATE_CC_STATE_POINTERS(&p->gpe,
+ p->gen6_3DSTATE_CC_STATE_POINTERS(p->dev,
p->state.BLEND_STATE,
p->state.DEPTH_STENCIL_STATE,
p->state.COLOR_CALC_STATE, p->cp);
if (session->sampler_state_vs_changed ||
session->sampler_state_gs_changed ||
session->sampler_state_fs_changed) {
- p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(&p->gpe,
+ p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(p->dev,
p->state.vs.SAMPLER_STATE,
0,
p->state.wm.SAMPLER_STATE, p->cp);
{
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_state_changed) {
- p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(&p->gpe,
+ p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
p->state.SCISSOR_RECT, p->cp);
}
if (session->binding_table_vs_changed ||
session->binding_table_gs_changed ||
session->binding_table_fs_changed) {
- p->gen6_3DSTATE_BINDING_TABLE_POINTERS(&p->gpe,
+ p->gen6_3DSTATE_BINDING_TABLE_POINTERS(p->dev,
p->state.vs.BINDING_TABLE_STATE,
p->state.gs.BINDING_TABLE_STATE,
p->state.wm.BINDING_TABLE_STATE, p->cp);
struct gen6_pipeline_session *session)
{
/* 3DSTATE_INDEX_BUFFER */
- if (DIRTY(INDEX_BUFFER)) {
- p->gen6_3DSTATE_INDEX_BUFFER(&p->gpe,
- &ilo->index_buffer, false, p->cp);
+ if (DIRTY(INDEX_BUFFER) || session->batch_bo_changed) {
+ p->gen6_3DSTATE_INDEX_BUFFER(p->dev,
+ &ilo->ib.state, session->info->primitive_restart, p->cp);
}
/* 3DSTATE_VERTEX_BUFFERS */
- if (DIRTY(VERTEX_BUFFERS)) {
- p->gen6_3DSTATE_VERTEX_BUFFERS(&p->gpe,
- ilo->vertex_buffers.buffers, NULL,
- (1 << ilo->vertex_buffers.num_buffers) - 1, p->cp);
+ if (DIRTY(VERTEX_BUFFERS) || DIRTY(VERTEX_ELEMENTS) ||
+ session->batch_bo_changed) {
+ p->gen6_3DSTATE_VERTEX_BUFFERS(p->dev,
+ ilo->vb.states, ilo->vb.enabled_mask, ilo->ve, p->cp);
}
/* 3DSTATE_VERTEX_ELEMENTS */
if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS)) {
- const struct ilo_vertex_element *ive = ilo->vertex_elements;
+ const struct ilo_ve_state *ve = ilo->ve;
bool last_velement_edgeflag = false;
bool prepend_generate_ids = false;
if (info->edgeflag_in >= 0) {
/* we rely on the state tracker here */
- assert(info->edgeflag_in == ive->num_elements - 1);
+ assert(info->edgeflag_in == ve->count - 1);
last_velement_edgeflag = true;
}
prepend_generate_ids = (info->has_instanceid || info->has_vertexid);
}
- p->gen6_3DSTATE_VERTEX_ELEMENTS(&p->gpe,
- ive->elements, ive->num_elements,
+ p->gen6_3DSTATE_VERTEX_ELEMENTS(p->dev, ve,
last_velement_edgeflag, prepend_generate_ids, p->cp);
}
}
{
/* 3DSTATE_VF_STATISTICS */
if (session->hw_ctx_changed)
- p->gen6_3DSTATE_VF_STATISTICS(&p->gpe, false, p->cp);
+ p->gen6_3DSTATE_VF_STATISTICS(p->dev, false, p->cp);
}
void
struct gen6_pipeline_session *session)
{
/* 3DPRIMITIVE */
- p->gen6_3DPRIMITIVE(&p->gpe, session->info, false, p->cp);
+ p->gen6_3DPRIMITIVE(p->dev, session->info, false, p->cp);
p->state.has_gen6_wa_pipe_control = false;
}
* the classic i965 does this in upload_vs_state(), citing a spec that I
* cannot find
*/
- if (emit_3dstate_vs && p->gen == ILO_GEN(6))
+ if (emit_3dstate_vs && p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
/* 3DSTATE_CONSTANT_VS */
if (emit_3dstate_constant_vs) {
- p->gen6_3DSTATE_CONSTANT_VS(&p->gpe,
+ p->gen6_3DSTATE_CONSTANT_VS(p->dev,
&p->state.vs.PUSH_CONSTANT_BUFFER,
&p->state.vs.PUSH_CONSTANT_BUFFER_size,
1, p->cp);
/* 3DSTATE_VS */
if (emit_3dstate_vs) {
const struct ilo_shader *vs = (ilo->vs)? ilo->vs->shader : NULL;
- const int num_samplers = ilo->samplers[PIPE_SHADER_VERTEX].num_samplers;
+ const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
- p->gen6_3DSTATE_VS(&p->gpe,
- vs, ilo->max_vs_threads, num_samplers, p->cp);
+ p->gen6_3DSTATE_VS(p->dev, vs, num_samplers, p->cp);
}
- if (emit_3dstate_constant_vs && p->gen == ILO_GEN(6))
+ if (emit_3dstate_constant_vs && p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_vs_const_flush(p);
}
{
/* 3DSTATE_CONSTANT_GS */
if (session->pcb_state_gs_changed)
- p->gen6_3DSTATE_CONSTANT_GS(&p->gpe, NULL, NULL, 0, p->cp);
+ p->gen6_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
/* 3DSTATE_GS */
if (DIRTY(GS) || DIRTY(VS) || session->prim_changed) {
if (gs)
assert(!gs->pcb.clip_state_size);
- p->gen6_3DSTATE_GS(&p->gpe,
- gs, ilo->max_gs_threads, vs,
+ p->gen6_3DSTATE_GS(p->dev, gs, vs,
(vs) ? vs->cache_offset + vs->gs_offsets[num_vertices - 1] : 0,
p->cp);
}
}
-static void
-gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
- const struct ilo_context *ilo,
- struct gen6_pipeline_session *session)
+bool
+gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p,
+ const struct ilo_context *ilo,
+ struct gen6_pipeline_session *session)
{
- /* 3DSTATE_GS_SVB_INDEX */
if (DIRTY(VS) || DIRTY(GS) || DIRTY(STREAM_OUTPUT_TARGETS)) {
const struct pipe_stream_output_info *so_info =
(ilo->gs) ? &ilo->gs->info.stream_output :
unsigned max_svbi = 0xffffffff;
int i;
- /* get max_svbi */
- for (i = 0; so_info && i < so_info->num_outputs; i++) {
+ for (i = 0; i < so_info->num_outputs; i++) {
const int output_buffer = so_info->output[i].output_buffer;
const struct pipe_stream_output_target *so =
- ilo->stream_output_targets.targets[output_buffer];
+ ilo->so.states[output_buffer];
const int struct_size = so_info->stride[output_buffer] * 4;
const int elem_size = so_info->output[i].num_components * 4;
int buf_size, count;
- if (!so)
- continue;
+ if (!so) {
+ max_svbi = 0;
+ break;
+ }
buf_size = so->buffer_size - so_info->output[i].dst_offset * 4;
max_svbi = count;
}
- if (p->gen == ILO_GEN(6))
+ if (p->state.so_max_vertices != max_svbi) {
+ p->state.so_max_vertices = max_svbi;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static void
+gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
+ const struct ilo_context *ilo,
+ struct gen6_pipeline_session *session)
+{
+ const bool emit = gen6_pipeline_update_max_svbi(p, ilo, session);
+
+ /* 3DSTATE_GS_SVB_INDEX */
+ if (emit) {
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_3DSTATE_GS_SVB_INDEX(&p->gpe,
- 0, p->state.so_num_vertices, max_svbi,
+ p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
+ 0, p->state.so_num_vertices, p->state.so_max_vertices,
false, p->cp);
if (session->hw_ctx_changed) {
+ int i;
+
/*
* From the Sandy Bridge PRM, volume 2 part 1, page 148:
*
* 0xFFFFFFFF in order to not cause overflow in that SVBI."
*/
for (i = 1; i < 4; i++) {
- p->gen6_3DSTATE_GS_SVB_INDEX(&p->gpe,
+ p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
i, 0, 0xffffffff, false, p->cp);
}
}
-
- /* remember the state for calculating primtive emitted in software */
- p->state.so_max_vertices = max_svbi;
}
}
/* 3DSTATE_CLIP */
if (DIRTY(RASTERIZER) || DIRTY(FS) ||
DIRTY(VIEWPORT) || DIRTY(FRAMEBUFFER)) {
- bool enable_guardband;
- float x1, x2, y1, y2;
+ bool enable_guardband = true;
+ unsigned i;
/*
* We do not do 2D clipping yet. Guard band test should only be enabled
* when the viewport is larger than the framebuffer.
*/
- x1 = fabs(ilo->viewport.scale[0]) * -1.0f + ilo->viewport.translate[0];
- x2 = fabs(ilo->viewport.scale[0]) * 1.0f + ilo->viewport.translate[0];
- y1 = fabs(ilo->viewport.scale[1]) * -1.0f + ilo->viewport.translate[1];
- y2 = fabs(ilo->viewport.scale[1]) * 1.0f + ilo->viewport.translate[1];
- enable_guardband =
- (x1 <= 0.0f && x2 >= (float) ilo->framebuffer.width &&
- y1 <= 0.0f && y2 >= (float) ilo->framebuffer.height);
-
- p->gen6_3DSTATE_CLIP(&p->gpe,
+ for (i = 0; i < ilo->viewport.count; i++) {
+ const struct ilo_viewport_cso *vp = &ilo->viewport.cso[i];
+
+ if (vp->min_x > 0.0f || vp->max_x < ilo->fb.state.width ||
+ vp->min_y > 0.0f || vp->max_y < ilo->fb.state.height) {
+ enable_guardband = false;
+ break;
+ }
+ }
+
+ p->gen6_3DSTATE_CLIP(p->dev,
ilo->rasterizer,
(ilo->fs && ilo->fs->shader->in.has_linear_interp),
enable_guardband, 1, p->cp);
(ilo->gs)? ilo->gs->shader :
(ilo->vs)? ilo->vs->shader : NULL;
- p->gen6_3DSTATE_SF(&p->gpe,
- ilo->rasterizer, fs, last_sh, p->cp);
+ p->gen6_3DSTATE_SF(p->dev, ilo->rasterizer, fs, last_sh, p->cp);
}
}
{
/* 3DSTATE_DRAWING_RECTANGLE */
if (DIRTY(FRAMEBUFFER)) {
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_3DSTATE_DRAWING_RECTANGLE(&p->gpe, 0, 0,
- ilo->framebuffer.width, ilo->framebuffer.height, p->cp);
+ p->gen6_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
+ ilo->fb.state.width, ilo->fb.state.height, p->cp);
}
}
{
/* 3DSTATE_CONSTANT_PS */
if (session->pcb_state_fs_changed)
- p->gen6_3DSTATE_CONSTANT_PS(&p->gpe, NULL, NULL, 0, p->cp);
+ p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
/* 3DSTATE_WM */
if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
DIRTY(RASTERIZER)) {
const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
- const int num_samplers =
- ilo->samplers[PIPE_SHADER_FRAGMENT].num_samplers;
- const bool dual_blend = (!ilo->blend->logicop_enable &&
- ilo->blend->rt[0].blend_enable &&
- util_blend_state_is_dual(ilo->blend, 0));
- const bool cc_may_kill = (ilo->depth_stencil_alpha->alpha.enabled ||
- ilo->blend->alpha_to_coverage);
+ const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
+ const bool dual_blend = ilo->blend->dual_blend;
+ const bool cc_may_kill = (ilo->dsa->alpha.enabled ||
+ ilo->blend->alpha_to_coverage);
if (fs)
assert(!fs->pcb.clip_state_size);
- if (p->gen == ILO_GEN(6) && session->hw_ctx_changed)
+ if (p->dev->gen == ILO_GEN(6) && session->hw_ctx_changed)
gen6_wa_pipe_control_wm_max_threads_stall(p);
- p->gen6_3DSTATE_WM(&p->gpe,
- fs, ilo->max_wm_threads, num_samplers,
- ilo->rasterizer, dual_blend, cc_may_kill, p->cp);
+ p->gen6_3DSTATE_WM(p->dev, fs, num_samplers,
+ &ilo->rasterizer->state, dual_blend, cc_may_kill, p->cp);
}
}
/* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
const uint32_t *packed_sample_pos;
- int num_samples = 1;
-
- if (ilo->framebuffer.nr_cbufs)
- num_samples = ilo->framebuffer.cbufs[0]->texture->nr_samples;
- packed_sample_pos = (num_samples > 1) ?
+ packed_sample_pos = (ilo->fb.num_samples > 1) ?
&p->packed_sample_position_4x : &p->packed_sample_position_1x;
- if (p->gen == ILO_GEN(6)) {
+ if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_multisample_flush(p);
}
- p->gen6_3DSTATE_MULTISAMPLE(&p->gpe, num_samples, packed_sample_pos,
- ilo->rasterizer->half_pixel_center, p->cp);
+ p->gen6_3DSTATE_MULTISAMPLE(p->dev,
+ ilo->fb.num_samples, packed_sample_pos,
+ ilo->rasterizer->state.half_pixel_center, p->cp);
- p->gen6_3DSTATE_SAMPLE_MASK(&p->gpe,
- (num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
+ p->gen6_3DSTATE_SAMPLE_MASK(p->dev,
+ (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
}
}
struct gen6_pipeline_session *session)
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FRAMEBUFFER)) {
- if (p->gen == ILO_GEN(6)) {
+ if (DIRTY(FRAMEBUFFER) || session->batch_bo_changed) {
+ if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_depth_flush(p);
}
- p->gen6_3DSTATE_DEPTH_BUFFER(&p->gpe,
- ilo->framebuffer.zsbuf, false, p->cp);
+ p->gen6_3DSTATE_DEPTH_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
/* TODO */
- p->gen6_3DSTATE_CLEAR_PARAMS(&p->gpe, 0, p->cp);
+ p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
}
}
{
/* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
- ilo->rasterizer->poly_stipple_enable) {
- if (p->gen == ILO_GEN(6))
+ ilo->rasterizer->state.poly_stipple_enable) {
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(&p->gpe,
+ p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(p->dev,
&ilo->poly_stipple, p->cp);
- p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(&p->gpe, 0, 0, p->cp);
+ p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(p->dev, 0, 0, p->cp);
}
/* 3DSTATE_LINE_STIPPLE */
- if (DIRTY(RASTERIZER) && ilo->rasterizer->line_stipple_enable) {
- if (p->gen == ILO_GEN(6))
+ if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_stipple_enable) {
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_3DSTATE_LINE_STIPPLE(&p->gpe,
- ilo->rasterizer->line_stipple_pattern,
- ilo->rasterizer->line_stipple_factor + 1, p->cp);
+ p->gen6_3DSTATE_LINE_STIPPLE(p->dev,
+ ilo->rasterizer->state.line_stipple_pattern,
+ ilo->rasterizer->state.line_stipple_factor + 1, p->cp);
}
/* 3DSTATE_AA_LINE_PARAMETERS */
- if (DIRTY(RASTERIZER) && ilo->rasterizer->line_smooth) {
- if (p->gen == ILO_GEN(6))
+ if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_smooth) {
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_3DSTATE_AA_LINE_PARAMETERS(&p->gpe, p->cp);
+ p->gen6_3DSTATE_AA_LINE_PARAMETERS(p->dev, p->cp);
}
}
const struct ilo_context *ilo,
struct gen6_pipeline_session *session)
{
+ /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
+ if (p->dev->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
+ p->state.SF_CLIP_VIEWPORT = p->gen7_SF_CLIP_VIEWPORT(p->dev,
+ ilo->viewport.cso, ilo->viewport.count, p->cp);
+
+ p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
+ ilo->viewport.cso, ilo->viewport.count, p->cp);
+
+ session->viewport_state_changed = true;
+ }
/* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
- if (DIRTY(VIEWPORT)) {
- p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(&p->gpe,
- &ilo->viewport, 1, p->cp);
+ else if (DIRTY(VIEWPORT)) {
+ p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(p->dev,
+ ilo->viewport.cso, ilo->viewport.count, p->cp);
- p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(&p->gpe,
- &ilo->viewport, 1, p->cp);
+ p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(p->dev,
+ ilo->viewport.cso, ilo->viewport.count, p->cp);
- p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(&p->gpe,
- &ilo->viewport, 1, p->cp);
+ p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
+ ilo->viewport.cso, ilo->viewport.count, p->cp);
session->viewport_state_changed = true;
}
{
/* BLEND_STATE */
if (DIRTY(BLEND) || DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA)) {
- p->state.BLEND_STATE = p->gen6_BLEND_STATE(&p->gpe,
- ilo->blend, &ilo->framebuffer,
- &ilo->depth_stencil_alpha->alpha, p->cp);
+ p->state.BLEND_STATE = p->gen6_BLEND_STATE(p->dev,
+ ilo->blend, &ilo->fb, &ilo->dsa->alpha, p->cp);
session->cc_state_blend_changed = true;
}
/* COLOR_CALC_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
- p->state.COLOR_CALC_STATE = p->gen6_COLOR_CALC_STATE(&p->gpe,
- &ilo->stencil_ref,
- ilo->depth_stencil_alpha->alpha.ref_value,
- &ilo->blend_color, p->cp);
+ p->state.COLOR_CALC_STATE =
+ p->gen6_COLOR_CALC_STATE(p->dev, &ilo->stencil_ref,
+ ilo->dsa->alpha.ref_value, &ilo->blend_color, p->cp);
session->cc_state_cc_changed = true;
}
/* DEPTH_STENCIL_STATE */
if (DIRTY(DEPTH_STENCIL_ALPHA)) {
p->state.DEPTH_STENCIL_STATE =
- p->gen6_DEPTH_STENCIL_STATE(&p->gpe,
- ilo->depth_stencil_alpha, p->cp);
+ p->gen6_DEPTH_STENCIL_STATE(p->dev, ilo->dsa, p->cp);
session->cc_state_dsa_changed = true;
}
struct gen6_pipeline_session *session)
{
/* SCISSOR_RECT */
- if (DIRTY(SCISSOR)) {
- p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(&p->gpe,
- &ilo->scissor, 1, p->cp);
+ if (DIRTY(SCISSOR) || DIRTY(VIEWPORT)) {
+ /* there should be as many scissors as there are viewports */
+ p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(p->dev,
+ &ilo->scissor, ilo->viewport.count, p->cp);
session->scissor_state_changed = true;
}
uint32_t *surface_state = &p->state.wm.SURFACE_STATE[offset];
int i;
- for (i = 0; i < ilo->framebuffer.nr_cbufs; i++) {
- const struct pipe_surface *surface = ilo->framebuffer.cbufs[i];
+ for (i = 0; i < ilo->fb.state.nr_cbufs; i++) {
+ const struct ilo_surface_cso *surface =
+ (const struct ilo_surface_cso *) ilo->fb.state.cbufs[i];
- assert(surface);
+ assert(surface && surface->is_rt);
surface_state[i] =
- p->gen6_surf_SURFACE_STATE(&p->gpe, surface, p->cp);
+ p->gen6_SURFACE_STATE(p->dev, &surface->u.rt, true, p->cp);
}
/*
* brw_update_renderbuffer_surfaces() does. I don't know why.
*/
if (i == 0) {
- struct pipe_surface null_surface;
+ struct ilo_view_surface null_surface;
- memset(&null_surface, 0, sizeof(null_surface));
- null_surface.width = ilo->framebuffer.width;
- null_surface.height = ilo->framebuffer.height;
+ ilo_gpe_init_view_surface_null(p->dev,
+ ilo->fb.state.width, ilo->fb.state.height,
+ 1, 0, &null_surface);
surface_state[i] =
- p->gen6_surf_SURFACE_STATE(&p->gpe, &null_surface, p->cp);
+ p->gen6_SURFACE_STATE(p->dev, &null_surface, true, p->cp);
i++;
}
const struct ilo_shader_state *vs = ilo->vs;
const struct ilo_shader_state *gs = ilo->gs;
const struct pipe_stream_output_target **so_targets =
- (const struct pipe_stream_output_target **)
- ilo->stream_output_targets.targets;
- const int num_so_targets = ilo->stream_output_targets.num_targets;
+ (const struct pipe_stream_output_target **) ilo->so.states;
+ const int num_so_targets = ilo->so.count;
- if (p->gen != ILO_GEN(6))
+ if (p->dev->gen != ILO_GEN(6))
return;
/* SURFACE_STATEs for stream output targets */
(target < num_so_targets) ? so_targets[target] : NULL;
if (so_target) {
- surface_state[i] = p->gen6_so_SURFACE_STATE(&p->gpe,
+ surface_state[i] = p->gen6_so_SURFACE_STATE(p->dev,
so_target, so_info, i, p->cp);
}
else {
int shader_type,
struct gen6_pipeline_session *session)
{
- const struct pipe_sampler_view **views =
- (const struct pipe_sampler_view **)
- ilo->sampler_views[shader_type].views;
- const int num_views = ilo->sampler_views[shader_type].num_views;
+ const struct pipe_sampler_view * const *views =
+ (const struct pipe_sampler_view **) ilo->view[shader_type].states;
+ const int num_views = ilo->view[shader_type].count;
uint32_t *surface_state;
int offset, i;
bool skip = false;
for (i = 0; i < num_views; i++) {
if (views[i]) {
+ const struct ilo_view_cso *cso =
+ (const struct ilo_view_cso *) views[i];
+
surface_state[i] =
- p->gen6_view_SURFACE_STATE(&p->gpe, views[i], p->cp);
+ p->gen6_SURFACE_STATE(p->dev, &cso->surface, false, p->cp);
}
else {
surface_state[i] = 0;
int shader_type,
struct gen6_pipeline_session *session)
{
- const struct pipe_constant_buffer *buffers =
- ilo->constant_buffers[shader_type].buffers;
- const int num_buffers = ilo->constant_buffers[shader_type].num_buffers;
+ const struct ilo_cbuf_cso *buffers = ilo->cbuf[shader_type].cso;
+ const int num_buffers = ilo->cbuf[shader_type].count;
uint32_t *surface_state;
int offset, i;
bool skip = false;
return;
for (i = 0; i < num_buffers; i++) {
- if (buffers[i].buffer) {
+ if (buffers[i].resource) {
+ const struct ilo_view_surface *surf = &buffers[i].surface;
+
surface_state[i] =
- p->gen6_cbuf_SURFACE_STATE(&p->gpe, &buffers[i], p->cp);
+ p->gen6_SURFACE_STATE(p->dev, surf, false, p->cp);
}
else {
surface_state[i] = 0;
if (size < session->num_surfaces[shader_type])
size = session->num_surfaces[shader_type];
- *binding_table_state = p->gen6_BINDING_TABLE_STATE(&p->gpe,
+ *binding_table_state = p->gen6_BINDING_TABLE_STATE(p->dev,
surface_state, size, p->cp);
*binding_table_state_size = size;
}
int shader_type,
struct gen6_pipeline_session *session)
{
- const struct pipe_sampler_state **samplers =
- (const struct pipe_sampler_state **)
- ilo->samplers[shader_type].samplers;
- const struct pipe_sampler_view **views =
- (const struct pipe_sampler_view **)
- ilo->sampler_views[shader_type].views;
- const int num_samplers = ilo->samplers[shader_type].num_samplers;
- const int num_views = ilo->sampler_views[shader_type].num_views;
+ const struct ilo_sampler_cso * const *samplers =
+ ilo->sampler[shader_type].cso;
+ const struct pipe_sampler_view * const *views =
+ (const struct pipe_sampler_view **) ilo->view[shader_type].states;
+ const int num_samplers = ilo->sampler[shader_type].count;
+ const int num_views = ilo->view[shader_type].count;
uint32_t *sampler_state, *border_color_state;
bool emit_border_color = false;
bool skip = false;
for (i = 0; i < num_samplers; i++) {
border_color_state[i] = (samplers[i]) ?
- p->gen6_SAMPLER_BORDER_COLOR_STATE(&p->gpe,
- &samplers[i]->border_color, p->cp) : 0;
+ p->gen6_SAMPLER_BORDER_COLOR_STATE(p->dev,
+ samplers[i], p->cp) : 0;
}
}
/* should we take the minimum of num_samplers and num_views? */
- *sampler_state = p->gen6_SAMPLER_STATE(&p->gpe,
+ *sampler_state = p->gen6_SAMPLER_STATE(p->dev,
samplers, views,
border_color_state,
MIN2(num_samplers, num_views), p->cp);
p->state.vs.PUSH_CONSTANT_BUFFER_size = vs->pcb.clip_state_size;
p->state.vs.PUSH_CONSTANT_BUFFER =
- p->gen6_push_constant_buffer(&p->gpe,
+ p->gen6_push_constant_buffer(p->dev,
p->state.vs.PUSH_CONSTANT_BUFFER_size, &pcb, p->cp);
memcpy(pcb, &ilo->clip, vs->pcb.clip_state_size);
if (session->hw_ctx_changed) {
/* these should be enough to make everything uploaded */
+ session->batch_bo_changed = true;
session->state_bo_changed = true;
session->instruction_bo_changed = true;
session->prim_changed = true;
}
else {
+ /*
+ * Any state that involves resources needs to be re-emitted when the
+ * batch bo changed. This is because we do not pin the resources and
+ * their offsets (or existence) may change between batch buffers.
+ *
+ * Since we messed around with ILO_3D_PIPELINE_INVALIDATE_BATCH_BO in
+ * handle_invalid_batch_bo(), use ILO_3D_PIPELINE_INVALIDATE_STATE_BO as
+ * a temporary workaround.
+ */
+ session->batch_bo_changed =
+ (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
+
session->state_bo_changed =
(p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
session->instruction_bo_changed =
void
ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
{
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, true);
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_WRITE_TIMESTAMP,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
true, p->cp);
ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
struct intel_bo *bo, int index)
{
- if (p->gen == ILO_GEN(6))
+ if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
- p->gen6_PIPE_CONTROL(&p->gpe,
+ p->gen6_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_DEPTH_COUNT,
bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
}
if (count)
- size += gen6->estimate_command_size(&p->gpe, cmd, count);
+ size += gen6->estimate_command_size(p->dev, cmd, count);
}
return size;
int i;
for (i = 0; i < Elements(static_states); i++) {
- static_size += gen6->estimate_state_size(&p->gpe,
+ static_size += gen6->estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
* sampler views (vs, fs)
* constant buffers (vs, fs)
*/
- count = ilo->framebuffer.nr_cbufs;
+ count = ilo->fb.state.nr_cbufs;
if (ilo->gs)
count += ilo->gs->info.stream_output.num_outputs;
count += ilo->vs->info.stream_output.num_outputs;
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- count += ilo->sampler_views[shader_type].num_views;
- count += ilo->constant_buffers[shader_type].num_buffers;
+ count += ilo->view[shader_type].count;
+ count += ilo->cbuf[shader_type].count;
}
if (count) {
- size += gen6->estimate_state_size(&p->gpe,
+ size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SURFACE_STATE, count);
}
/* samplers (vs, fs) */
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- count = ilo->samplers[shader_type].num_samplers;
+ count = ilo->sampler[shader_type].count;
if (count) {
- size += gen6->estimate_state_size(&p->gpe,
+ size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE, count);
- size += gen6->estimate_state_size(&p->gpe,
+ size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_SAMPLER_STATE, count);
}
}
if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
- size += gen6->estimate_state_size(&p->gpe,
+ size += gen6->estimate_state_size(p->dev,
ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER, pcb_size);
}
}
break;
case ILO_3D_PIPELINE_FLUSH:
- size = gen6->estimate_command_size(&p->gpe,
+ size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
- size = gen6->estimate_command_size(&p->gpe,
+ size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 2;
break;
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
- size = gen6->estimate_command_size(&p->gpe,
+ size = gen6->estimate_command_size(p->dev,
ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
break;
default:
GEN6_USE(p, DEPTH_STENCIL_STATE, gen6);
GEN6_USE(p, SCISSOR_RECT, gen6);
GEN6_USE(p, BINDING_TABLE_STATE, gen6);
- GEN6_USE(p, surf_SURFACE_STATE, gen6);
- GEN6_USE(p, view_SURFACE_STATE, gen6);
- GEN6_USE(p, cbuf_SURFACE_STATE, gen6);
+ GEN6_USE(p, SURFACE_STATE, gen6);
GEN6_USE(p, so_SURFACE_STATE, gen6);
GEN6_USE(p, SAMPLER_STATE, gen6);
GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen6);
projects / mesa.git / blobdiff