#include "util/u_dual_blend.h"
#include "intel_reg.h"
-#include "ilo_common.h"
+#include "ilo_blitter.h"
#include "ilo_context.h"
#include "ilo_cp.h"
#include "ilo_gpe_gen7.h"
struct intel_bo *bo = NULL;
uint32_t dw1 = PIPE_CONTROL_CS_STALL;
- assert(p->dev->gen == ILO_GEN(7));
+ assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
/* emit once */
if (p->state.has_gen6_wa_pipe_control)
bo = p->workaround_bo;
}
- p->gen6_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
+ gen6_emit_PIPE_CONTROL(p->dev, dw1, bo, 0, false, p->cp);
}
static void
gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
{
- assert(p->dev->gen == ILO_GEN(7));
+ assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 106:
* 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
* needs to be sent before any combination of VS associated 3DSTATE."
*/
- p->gen6_PIPE_CONTROL(p->dev,
+ gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_WRITE_IMMEDIATE,
p->workaround_bo, 0, false, p->cp);
gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
bool change_depth_buffer)
{
- assert(p->dev->gen == ILO_GEN(7));
+ assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 276:
* guarantee that the pipeline from WM onwards is already flushed
* (e.g., via a preceding MI_FLUSH)."
*/
- p->gen6_PIPE_CONTROL(p->dev,
+ gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
if (!change_depth_buffer)
return;
- p->gen6_PIPE_CONTROL(p->dev,
+ gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_CACHE_FLUSH,
NULL, 0, false, p->cp);
- p->gen6_PIPE_CONTROL(p->dev,
+ gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_DEPTH_STALL,
NULL, 0, false, p->cp);
}
static void
-gen7_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
+gen7_wa_pipe_control_ps_max_threads_stall(struct ilo_3d_pipeline *p)
{
- assert(p->dev->gen == ILO_GEN(7));
+ assert(p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5));
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 286:
*
- * "If this field (Maximum Number of Threads in 3DSTATE_WM) is changed
+ * "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
* between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
* Pixel Scoreboard set is required to be issued."
*/
- p->gen6_PIPE_CONTROL(p->dev,
+ gen6_emit_PIPE_CONTROL(p->dev,
PIPE_CONTROL_STALL_AT_SCOREBOARD,
NULL, 0, false, p->cp);
struct gen6_pipeline_session *session)
{
/* 3DSTATE_URB_{VS,GS,HS,DS} */
- if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS)) {
- const struct ilo_shader *vs = (ilo->vs) ? ilo->vs->shader : NULL;
+ if (DIRTY(VE) || DIRTY(VS)) {
/* the first 16KB are reserved for VS and PS PCBs */
- const int offset = 16 * 1024;
+ const int offset =
+ (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
int vs_entry_size, vs_total_size;
- vs_entry_size = (vs) ? vs->out.count : 0;
+ vs_entry_size = (ilo->vs) ?
+ ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
/*
* From the Ivy Bridge PRM, volume 2 part 1, page 35:
* Allocation Size must be sized to the maximum of the vertex input
* and output structures."
*/
- if (vs_entry_size < ilo->vertex_elements->num_elements)
- vs_entry_size = ilo->vertex_elements->num_elements;
+ if (vs_entry_size < ilo->ve->count)
+ vs_entry_size = ilo->ve->count;
vs_entry_size *= sizeof(float) * 4;
vs_total_size = ilo->dev->urb_size - offset;
gen7_wa_pipe_control_vs_depth_stall(p);
- p->gen7_3DSTATE_URB_VS(p->dev,
+ gen7_emit_3DSTATE_URB_VS(p->dev,
offset, vs_total_size, vs_entry_size, p->cp);
- p->gen7_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
- p->gen7_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
- p->gen7_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
+ gen7_emit_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
+ gen7_emit_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
+ gen7_emit_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
}
}
/* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
if (session->hw_ctx_changed) {
/*
- * push constant buffers are only allowed to take up at most the first
- * 16KB of the URB
+ * Push constant buffers are only allowed to take up at most the first
+ * 16KB of the URB. Split the space evenly for VS and FS.
*/
- p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev,
- 0, 8192, p->cp);
+ const int max_size =
+ (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
+ const int size = max_size / 2;
+ int offset = 0;
- p->gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev,
- 8192, 8192, p->cp);
+ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev, offset, size, p->cp);
+ offset += size;
- gen7_wa_pipe_control_cs_stall(p, true, true);
+ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev, offset, size, p->cp);
+
+ if (p->dev->gen == ILO_GEN(7))
+ gen7_wa_pipe_control_cs_stall(p, true, true);
}
}
{
/* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
if (session->viewport_state_changed) {
- p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
+ gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
p->state.CC_VIEWPORT, p->cp);
- p->gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
+ gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->dev,
p->state.SF_CLIP_VIEWPORT, p->cp);
}
}
{
/* 3DSTATE_BLEND_STATE_POINTERS */
if (session->cc_state_blend_changed) {
- p->gen7_3DSTATE_BLEND_STATE_POINTERS(p->dev,
+ gen7_emit_3DSTATE_BLEND_STATE_POINTERS(p->dev,
p->state.BLEND_STATE, p->cp);
}
/* 3DSTATE_CC_STATE_POINTERS */
if (session->cc_state_cc_changed) {
- p->gen7_3DSTATE_CC_STATE_POINTERS(p->dev,
+ gen7_emit_3DSTATE_CC_STATE_POINTERS(p->dev,
p->state.COLOR_CALC_STATE, p->cp);
}
/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
if (session->cc_state_dsa_changed) {
- p->gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
+ gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
p->state.DEPTH_STENCIL_STATE, p->cp);
}
}
const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
/* see gen6_pipeline_vs() */
const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
- const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(VERTEX_SAMPLERS));
+ const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
+ session->kernel_bo_changed);
/* emit depth stall before any of the VS commands */
if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
- emit_3dstate_constant_vs || emit_3dstate_vs)
- gen7_wa_pipe_control_vs_depth_stall(p);
+ emit_3dstate_constant_vs || emit_3dstate_vs)
+ gen7_wa_pipe_control_vs_depth_stall(p);
/* 3DSTATE_BINDING_TABLE_POINTERS_VS */
if (emit_3dstate_binding_table) {
- p->gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
- p->state.vs.BINDING_TABLE_STATE, p->cp);
+ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_VS(p->dev,
+ p->state.vs.BINDING_TABLE_STATE, p->cp);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
if (emit_3dstate_sampler_state) {
- p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
- p->state.vs.SAMPLER_STATE, p->cp);
+ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->dev,
+ p->state.vs.SAMPLER_STATE, p->cp);
+ }
+
+ /* 3DSTATE_CONSTANT_VS */
+ if (emit_3dstate_constant_vs) {
+ gen7_emit_3DSTATE_CONSTANT_VS(p->dev,
+ &p->state.vs.PUSH_CONSTANT_BUFFER,
+ &p->state.vs.PUSH_CONSTANT_BUFFER_size,
+ 1, p->cp);
}
- gen6_pipeline_vs(p, ilo, session);
+ /* 3DSTATE_VS */
+ if (emit_3dstate_vs) {
+ const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
+
+ gen6_emit_3DSTATE_VS(p->dev, ilo->vs, num_samplers, p->cp);
+ }
}
static void
{
/* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
if (session->hw_ctx_changed) {
- p->gen7_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
- p->gen7_3DSTATE_HS(p->dev, NULL, 0, 0, p->cp);
+ gen7_emit_3DSTATE_CONSTANT_HS(p->dev, 0, 0, 0, p->cp);
+ gen7_emit_3DSTATE_HS(p->dev, NULL, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_HS */
if (session->hw_ctx_changed)
- p->gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
+ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_HS(p->dev, 0, p->cp);
}
static void
{
/* 3DSTATE_TE */
if (session->hw_ctx_changed)
- p->gen7_3DSTATE_TE(p->dev, p->cp);
+ gen7_emit_3DSTATE_TE(p->dev, p->cp);
}
static void
{
/* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
if (session->hw_ctx_changed) {
- p->gen7_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
- p->gen7_3DSTATE_DS(p->dev, NULL, 0, 0, p->cp);
+ gen7_emit_3DSTATE_CONSTANT_DS(p->dev, 0, 0, 0, p->cp);
+ gen7_emit_3DSTATE_DS(p->dev, NULL, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_DS */
if (session->hw_ctx_changed)
- p->gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
+ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_DS(p->dev, 0, p->cp);
}
{
/* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
if (session->hw_ctx_changed) {
- p->gen6_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
- p->gen7_3DSTATE_GS(p->dev, NULL, 0, p->cp);
+ gen7_emit_3DSTATE_CONSTANT_GS(p->dev, 0, 0, 0, p->cp);
+ gen7_emit_3DSTATE_GS(p->dev, NULL, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_GS */
if (session->binding_table_gs_changed) {
- p->gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
+ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_GS(p->dev,
p->state.gs.BINDING_TABLE_STATE, p->cp);
}
}
struct gen6_pipeline_session *session)
{
const struct pipe_stream_output_info *so_info;
- const struct ilo_shader *sh;
+ const struct ilo_shader_state *shader;
bool dirty_sh = false;
if (ilo->gs) {
- so_info = &ilo->gs->info.stream_output;
- sh = ilo->gs->shader;
+ shader = ilo->gs;
dirty_sh = DIRTY(GS);
}
- else if (ilo->vs) {
- so_info = &ilo->vs->info.stream_output;
- sh = ilo->vs->shader;
+ else {
+ shader = ilo->vs;
dirty_sh = DIRTY(VS);
}
+ so_info = ilo_shader_get_kernel_so_info(shader);
+
gen6_pipeline_update_max_svbi(p, ilo, session);
/* 3DSTATE_SO_BUFFER */
- if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) &&
- ilo->stream_output_targets.num_targets) {
+ if ((DIRTY(SO) || dirty_sh || session->batch_bo_changed) &&
+ ilo->so.enabled) {
int i;
- for (i = 0; i < ilo->stream_output_targets.num_targets; i++) {
+ for (i = 0; i < ilo->so.count; i++) {
const int stride = so_info->stride[i] * 4; /* in bytes */
int base = 0;
- /* reset HW write offsets and offset buffer base */
- if (!p->cp->render_ctx) {
- ilo_cp_set_one_off_flags(p->cp, INTEL_EXEC_GEN7_SOL_RESET);
- base += p->state.so_num_vertices * stride;
- }
-
- p->gen7_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
- ilo->stream_output_targets.targets[i], p->cp);
+ gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, base, stride,
+ ilo->so.states[i], p->cp);
}
for (; i < 4; i++)
- p->gen7_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
+ gen7_emit_3DSTATE_SO_BUFFER(p->dev, i, 0, 0, NULL, p->cp);
}
/* 3DSTATE_SO_DECL_LIST */
- if (dirty_sh && ilo->stream_output_targets.num_targets)
- p->gen7_3DSTATE_SO_DECL_LIST(p->dev, so_info, sh, p->cp);
+ if (dirty_sh && ilo->so.enabled)
+ gen7_emit_3DSTATE_SO_DECL_LIST(p->dev, so_info, p->cp);
/* 3DSTATE_STREAMOUT */
- if (DIRTY(STREAM_OUTPUT_TARGETS) || DIRTY(RASTERIZER) || dirty_sh) {
- const unsigned buffer_mask =
- (1 << ilo->stream_output_targets.num_targets) - 1;
+ if (DIRTY(SO) || DIRTY(RASTERIZER) || dirty_sh) {
+ const unsigned buffer_mask = (1 << ilo->so.count) - 1;
+ const int output_count = ilo_shader_get_kernel_param(shader,
+ ILO_KERNEL_OUTPUT_COUNT);
- p->gen7_3DSTATE_STREAMOUT(p->dev, buffer_mask, sh->out.count,
- ilo->rasterizer->rasterizer_discard, p->cp);
+ gen7_emit_3DSTATE_STREAMOUT(p->dev, buffer_mask, output_count,
+ ilo->rasterizer->state.rasterizer_discard, p->cp);
}
}
struct gen6_pipeline_session *session)
{
/* 3DSTATE_SBE */
- if (DIRTY(RASTERIZER) || DIRTY(VS) || DIRTY(GS) || DIRTY(FS)) {
- const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
- const struct ilo_shader *last_sh =
- (ilo->gs)? ilo->gs->shader :
- (ilo->vs)? ilo->vs->shader : NULL;
-
- p->gen7_3DSTATE_SBE(p->dev,
- ilo->rasterizer, fs, last_sh, p->cp);
- }
+ if (DIRTY(RASTERIZER) || DIRTY(FS))
+ gen7_emit_3DSTATE_SBE(p->dev, ilo->rasterizer, ilo->fs, ilo->cp);
/* 3DSTATE_SF */
- if (DIRTY(RASTERIZER) || DIRTY(FRAMEBUFFER)) {
- gen7_wa_pipe_control_cs_stall(p, true, true);
+ if (DIRTY(RASTERIZER) || DIRTY(FB)) {
+ struct pipe_surface *zs = ilo->fb.state.zsbuf;
- p->gen7_3DSTATE_SF(p->dev,
- ilo->rasterizer, ilo->framebuffer.zsbuf, p->cp);
+ gen7_wa_pipe_control_cs_stall(p, true, true);
+ gen7_emit_3DSTATE_SF(p->dev, ilo->rasterizer,
+ (zs) ? zs->format : PIPE_FORMAT_NONE, p->cp);
}
}
struct gen6_pipeline_session *session)
{
/* 3DSTATE_WM */
- if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
- DIRTY(RASTERIZER)) {
- const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
- const bool cc_may_kill = (ilo->depth_stencil_alpha->alpha.enabled ||
- ilo->blend->alpha_to_coverage);
+ if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DSA) || DIRTY(RASTERIZER)) {
+ const bool cc_may_kill = (ilo->dsa->dw_alpha ||
+ ilo->blend->alpha_to_coverage);
- if (fs)
- assert(!fs->pcb.clip_state_size);
-
- if (p->dev->gen == ILO_GEN(7) && session->hw_ctx_changed)
- gen7_wa_pipe_control_wm_max_threads_stall(p);
-
- p->gen7_3DSTATE_WM(p->dev,
- fs, ilo->rasterizer, cc_may_kill, p->cp);
+ gen7_emit_3DSTATE_WM(p->dev, ilo->fs,
+ ilo->rasterizer, cc_may_kill, 0, p->cp);
}
/* 3DSTATE_BINDING_TABLE_POINTERS_PS */
if (session->binding_table_fs_changed) {
- p->gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
+ gen7_emit_3DSTATE_BINDING_TABLE_POINTERS_PS(p->dev,
p->state.wm.BINDING_TABLE_STATE, p->cp);
}
/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
if (session->sampler_state_fs_changed) {
- p->gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
+ gen7_emit_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->dev,
p->state.wm.SAMPLER_STATE, p->cp);
}
/* 3DSTATE_CONSTANT_PS */
- if (session->pcb_state_fs_changed)
- p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
+ if (session->pcb_state_fs_changed) {
+ gen7_emit_3DSTATE_CONSTANT_PS(p->dev,
+ &p->state.wm.PUSH_CONSTANT_BUFFER,
+ &p->state.wm.PUSH_CONSTANT_BUFFER_size,
+ 1, p->cp);
+ }
/* 3DSTATE_PS */
- if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
- DIRTY(BLEND)) {
- const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
- const int num_samplers =
- ilo->samplers[PIPE_SHADER_FRAGMENT].num_samplers;
- const bool dual_blend = (!ilo->blend->logicop_enable &&
- ilo->blend->rt[0].blend_enable &&
- util_blend_state_is_dual(ilo->blend, 0));
+ if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) ||
+ session->kernel_bo_changed) {
+ const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
+ const bool dual_blend = ilo->blend->dual_blend;
- if (fs)
- assert(!fs->pcb.clip_state_size);
+ if ((p->dev->gen == ILO_GEN(7) || p->dev->gen == ILO_GEN(7.5)) &&
+ session->hw_ctx_changed)
+ gen7_wa_pipe_control_ps_max_threads_stall(p);
- p->gen7_3DSTATE_PS(p->dev, fs, num_samplers, dual_blend, p->cp);
+ gen7_emit_3DSTATE_PS(p->dev, ilo->fs, num_samplers, dual_blend, p->cp);
}
/* 3DSTATE_SCISSOR_STATE_POINTERS */
if (session->scissor_state_changed) {
- p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
+ gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
p->state.SCISSOR_RECT, p->cp);
}
/* XXX what is the best way to know if this workaround is needed? */
{
- const bool emit_3dstate_ps = (DIRTY(FS) ||
- DIRTY(FRAGMENT_SAMPLERS) ||
- DIRTY(BLEND));
+ const bool emit_3dstate_ps =
+ (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND));
const bool emit_3dstate_depth_buffer =
- (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
- session->state_bo_changed);
+ (DIRTY(FB) || DIRTY(DSA) || session->state_bo_changed);
if (emit_3dstate_ps ||
emit_3dstate_depth_buffer ||
gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
}
- /*
- * glCopyPixels() with GL_DEPTH, which flushes the context before copying
- * the depth buffer to a temporary texture, could not update the depth
- * buffer _sometimes_. Reissuing 3DSTATE_DEPTH_BUFFER in the new batch
- * makes the problem gone.
- */
-
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA) ||
- session->state_bo_changed) {
- const bool hiz = false;
-
- p->gen7_3DSTATE_DEPTH_BUFFER(p->dev,
- ilo->framebuffer.zsbuf,
- ilo->depth_stencil_alpha,
- hiz, p->cp);
-
- p->gen6_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
- (hiz) ? ilo->framebuffer.zsbuf : NULL, p->cp);
-
- p->gen6_3DSTATE_STENCIL_BUFFER(p->dev, ilo->framebuffer.zsbuf, p->cp);
+ if (DIRTY(FB) || session->batch_bo_changed) {
+ const struct ilo_zs_surface *zs;
+ uint32_t clear_params;
+
+ if (ilo->fb.state.zsbuf) {
+ const struct ilo_surface_cso *surface =
+ (const struct ilo_surface_cso *) ilo->fb.state.zsbuf;
+ const struct ilo_texture_slice *slice =
+ ilo_texture_get_slice(ilo_texture(surface->base.texture),
+ surface->base.u.tex.level, surface->base.u.tex.first_layer);
+
+ assert(!surface->is_rt);
+ zs = &surface->u.zs;
+ clear_params = slice->clear_value;
+ }
+ else {
+ zs = &ilo->fb.null_zs;
+ clear_params = 0;
+ }
- /* TODO */
- p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
+ gen6_emit_3DSTATE_DEPTH_BUFFER(p->dev, zs, p->cp);
+ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p->dev, zs, p->cp);
+ gen6_emit_3DSTATE_STENCIL_BUFFER(p->dev, zs, p->cp);
+ gen7_emit_3DSTATE_CLEAR_PARAMS(p->dev, clear_params, p->cp);
}
}
struct gen6_pipeline_session *session)
{
/* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
- if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
+ if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
const uint32_t *packed_sample_pos;
- int num_samples = 1;
gen7_wa_pipe_control_cs_stall(p, true, true);
- if (ilo->framebuffer.nr_cbufs)
- num_samples = ilo->framebuffer.cbufs[0]->texture->nr_samples;
-
packed_sample_pos =
- (num_samples > 4) ? p->packed_sample_position_8x :
- (num_samples > 1) ? &p->packed_sample_position_4x :
+ (ilo->fb.num_samples > 4) ? p->packed_sample_position_8x :
+ (ilo->fb.num_samples > 1) ? &p->packed_sample_position_4x :
&p->packed_sample_position_1x;
- p->gen6_3DSTATE_MULTISAMPLE(p->dev, num_samples, packed_sample_pos,
- ilo->rasterizer->half_pixel_center, p->cp);
+ gen6_emit_3DSTATE_MULTISAMPLE(p->dev,
+ ilo->fb.num_samples, packed_sample_pos,
+ ilo->rasterizer->state.half_pixel_center, p->cp);
- p->gen7_3DSTATE_SAMPLE_MASK(p->dev,
- (num_samples > 1) ? ilo->sample_mask : 0x1,
- num_samples, p->cp);
+ gen7_emit_3DSTATE_SAMPLE_MASK(p->dev,
+ (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1,
+ ilo->fb.num_samples, p->cp);
}
}
+static void
+gen7_pipeline_vf_draw(struct ilo_3d_pipeline *p,
+ const struct ilo_context *ilo,
+ struct gen6_pipeline_session *session)
+{
+ /* 3DPRIMITIVE */
+ gen7_emit_3DPRIMITIVE(p->dev, ilo->draw, &ilo->ib, false, p->cp);
+ p->state.has_gen6_wa_pipe_control = false;
+}
+
static void
gen7_pipeline_commands(struct ilo_3d_pipeline *p,
const struct ilo_context *ilo,
gen6_pipeline_wm_raster(p, ilo, session);
gen6_pipeline_sf_rect(p, ilo, session);
gen6_pipeline_vf(p, ilo, session);
- gen6_pipeline_vf_draw(p, ilo, session);
+ gen7_pipeline_vf_draw(p, ilo, session);
}
static void
ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
- const struct ilo_context *ilo,
- const struct pipe_draw_info *info)
+ const struct ilo_context *ilo)
{
struct gen6_pipeline_session session;
- gen6_pipeline_prepare(p, ilo, info, &session);
+ gen6_pipeline_prepare(p, ilo, &session);
session.emit_draw_states = gen6_pipeline_states;
session.emit_draw_commands = gen7_pipeline_commands;
gen6_pipeline_end(p, ilo, &session);
}
+static void
+gen7_rectlist_pcb_alloc(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ /*
+ * Push constant buffers are only allowed to take up at most the first
+ * 16KB of the URB. Split the space evenly for VS and FS.
+ */
+ const int max_size =
+ (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
+ const int size = max_size / 2;
+ int offset = 0;
+
+ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->dev, offset, size, p->cp);
+ offset += size;
+
+ gen7_emit_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->dev, offset, size, p->cp);
+
+ gen7_wa_pipe_control_cs_stall(p, true, true);
+}
+
+static void
+gen7_rectlist_urb(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ /* the first 16KB are reserved for VS and PS PCBs */
+ const int offset =
+ (p->dev->gen == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
+
+ gen7_emit_3DSTATE_URB_VS(p->dev, offset, p->dev->urb_size - offset,
+ blitter->ve.count * 4 * sizeof(float), p->cp);
+
+ gen7_emit_3DSTATE_URB_GS(p->dev, offset, 0, 0, p->cp);
+ gen7_emit_3DSTATE_URB_HS(p->dev, offset, 0, 0, p->cp);
+ gen7_emit_3DSTATE_URB_DS(p->dev, offset, 0, 0, p->cp);
+}
+
+static void
+gen7_rectlist_vs_to_sf(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ gen7_emit_3DSTATE_CONSTANT_VS(p->dev, NULL, NULL, 0, p->cp);
+ gen6_emit_3DSTATE_VS(p->dev, NULL, 0, p->cp);
+
+ gen7_emit_3DSTATE_CONSTANT_HS(p->dev, NULL, NULL, 0, p->cp);
+ gen7_emit_3DSTATE_HS(p->dev, NULL, 0, p->cp);
+
+ gen7_emit_3DSTATE_TE(p->dev, p->cp);
+
+ gen7_emit_3DSTATE_CONSTANT_DS(p->dev, NULL, NULL, 0, p->cp);
+ gen7_emit_3DSTATE_DS(p->dev, NULL, 0, p->cp);
+
+ gen7_emit_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
+ gen7_emit_3DSTATE_GS(p->dev, NULL, 0, p->cp);
+
+ gen7_emit_3DSTATE_STREAMOUT(p->dev, 0x0, 0, false, p->cp);
+
+ gen6_emit_3DSTATE_CLIP(p->dev, NULL, NULL, false, 0, p->cp);
+
+ gen7_wa_pipe_control_cs_stall(p, true, true);
+
+ gen7_emit_3DSTATE_SF(p->dev, NULL, blitter->fb.dst.base.format, p->cp);
+ gen7_emit_3DSTATE_SBE(p->dev, NULL, NULL, p->cp);
+}
+
+static void
+gen7_rectlist_wm(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ uint32_t hiz_op;
+
+ switch (blitter->op) {
+ case ILO_BLITTER_RECTLIST_CLEAR_ZS:
+ hiz_op = GEN7_WM_DEPTH_CLEAR;
+ break;
+ case ILO_BLITTER_RECTLIST_RESOLVE_Z:
+ hiz_op = GEN7_WM_DEPTH_RESOLVE;
+ break;
+ case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
+ hiz_op = GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
+ break;
+ default:
+ hiz_op = 0;
+ break;
+ }
+
+ gen7_emit_3DSTATE_WM(p->dev, NULL, NULL, false, hiz_op, p->cp);
+
+ gen7_emit_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
+
+ gen7_wa_pipe_control_ps_max_threads_stall(p);
+ gen7_emit_3DSTATE_PS(p->dev, NULL, 0, false, p->cp);
+}
+
+static void
+gen7_rectlist_wm_depth(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ gen7_wa_pipe_control_wm_depth_stall(p, true);
+
+ if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
+ ILO_BLITTER_USE_FB_STENCIL)) {
+ gen6_emit_3DSTATE_DEPTH_BUFFER(p->dev,
+ &blitter->fb.dst.u.zs, p->cp);
+ }
+
+ if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
+ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(p->dev,
+ &blitter->fb.dst.u.zs, p->cp);
+ }
+
+ if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
+ gen6_emit_3DSTATE_STENCIL_BUFFER(p->dev,
+ &blitter->fb.dst.u.zs, p->cp);
+ }
+
+ gen7_emit_3DSTATE_CLEAR_PARAMS(p->dev,
+ blitter->depth_clear_value, p->cp);
+}
+
+static void
+gen7_rectlist_wm_multisample(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ const uint32_t *packed_sample_pos =
+ (blitter->fb.num_samples > 4) ? p->packed_sample_position_8x :
+ (blitter->fb.num_samples > 1) ? &p->packed_sample_position_4x :
+ &p->packed_sample_position_1x;
+
+ gen7_wa_pipe_control_cs_stall(p, true, true);
+
+ gen6_emit_3DSTATE_MULTISAMPLE(p->dev, blitter->fb.num_samples,
+ packed_sample_pos, true, p->cp);
+
+ gen7_emit_3DSTATE_SAMPLE_MASK(p->dev,
+ (1 << blitter->fb.num_samples) - 1, blitter->fb.num_samples, p->cp);
+}
+
+static void
+gen7_rectlist_commands(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ gen7_rectlist_wm_multisample(p, blitter, session);
+
+ gen6_emit_STATE_BASE_ADDRESS(p->dev,
+ NULL, /* General State Base */
+ p->cp->bo, /* Surface State Base */
+ p->cp->bo, /* Dynamic State Base */
+ NULL, /* Indirect Object Base */
+ NULL, /* Instruction Base */
+ 0, 0, 0, 0, p->cp);
+
+ gen6_emit_3DSTATE_VERTEX_BUFFERS(p->dev,
+ &blitter->ve, &blitter->vb, p->cp);
+
+ gen6_emit_3DSTATE_VERTEX_ELEMENTS(p->dev,
+ &blitter->ve, false, false, p->cp);
+
+ gen7_rectlist_pcb_alloc(p, blitter, session);
+
+ /* needed for any VS-related commands */
+ gen7_wa_pipe_control_vs_depth_stall(p);
+
+ gen7_rectlist_urb(p, blitter, session);
+
+ if (blitter->uses & ILO_BLITTER_USE_DSA) {
+ gen7_emit_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->dev,
+ session->DEPTH_STENCIL_STATE, p->cp);
+ }
+
+ if (blitter->uses & ILO_BLITTER_USE_CC) {
+ gen7_emit_3DSTATE_CC_STATE_POINTERS(p->dev,
+ session->COLOR_CALC_STATE, p->cp);
+ }
+
+ gen7_rectlist_vs_to_sf(p, blitter, session);
+ gen7_rectlist_wm(p, blitter, session);
+
+ if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
+ gen7_emit_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->dev,
+ session->CC_VIEWPORT, p->cp);
+ }
+
+ gen7_rectlist_wm_depth(p, blitter, session);
+
+ gen6_emit_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
+ blitter->fb.width, blitter->fb.height, p->cp);
+
+ gen7_emit_3DPRIMITIVE(p->dev, &blitter->draw, NULL, true, p->cp);
+}
+
+static void
+gen7_rectlist_states(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter,
+ struct gen6_rectlist_session *session)
+{
+ if (blitter->uses & ILO_BLITTER_USE_DSA) {
+ session->DEPTH_STENCIL_STATE =
+ gen6_emit_DEPTH_STENCIL_STATE(p->dev, &blitter->dsa, p->cp);
+ }
+
+ if (blitter->uses & ILO_BLITTER_USE_CC) {
+ session->COLOR_CALC_STATE =
+ gen6_emit_COLOR_CALC_STATE(p->dev, &blitter->cc.stencil_ref,
+ blitter->cc.alpha_ref, &blitter->cc.blend_color, p->cp);
+ }
+
+ if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
+ session->CC_VIEWPORT =
+ gen6_emit_CC_VIEWPORT(p->dev, &blitter->viewport, 1, p->cp);
+ }
+}
+
+static void
+ilo_3d_pipeline_emit_rectlist_gen7(struct ilo_3d_pipeline *p,
+ const struct ilo_blitter *blitter)
+{
+ struct gen6_rectlist_session session;
+
+ memset(&session, 0, sizeof(session));
+ gen7_rectlist_states(p, blitter, &session);
+ gen7_rectlist_commands(p, blitter, &session);
+}
+
static int
gen7_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen7 *gen7,
const struct ilo_context *ilo)
{
static int size;
}
if (count) {
- size += gen7->estimate_command_size(p->dev,
+ size += ilo_gpe_gen7_estimate_command_size(p->dev,
cmd, count);
}
}
static int
gen7_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
- const struct ilo_gpe_gen7 *gen7,
const struct ilo_context *ilo)
{
static int static_size;
int i;
for (i = 0; i < Elements(static_states); i++) {
- static_size += gen7->estimate_state_size(p->dev,
+ static_size += ilo_gpe_gen7_estimate_state_size(p->dev,
static_states[i].state,
static_states[i].count);
}
* sampler views (vs, fs)
* constant buffers (vs, fs)
*/
- count = ilo->framebuffer.nr_cbufs;
+ count = ilo->fb.state.nr_cbufs;
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- count += ilo->sampler_views[shader_type].num_views;
- count += ilo->constant_buffers[shader_type].num_buffers;
+ count += ilo->view[shader_type].count;
+ count += util_bitcount(ilo->cbuf[shader_type].enabled_mask);
}
if (count) {
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SURFACE_STATE, count);
}
/* samplers (vs, fs) */
for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
- count = ilo->samplers[shader_type].num_samplers;
+ count = ilo->sampler[shader_type].count;
if (count) {
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_BORDER_COLOR_STATE, count);
- size += gen7->estimate_state_size(p->dev,
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
ILO_GPE_GEN7_SAMPLER_STATE, count);
}
}
/* pcb (vs) */
- if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
- const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
+ if (ilo->vs) {
+ const int cbuf0_size =
+ ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_PCB_CBUF0_SIZE);
+ const int ucp_size =
+ ilo_shader_get_kernel_param(ilo->vs, ILO_KERNEL_VS_PCB_UCP_SIZE);
+
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
+ ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, cbuf0_size + ucp_size);
+ }
+
+ /* pcb (fs) */
+ if (ilo->fs) {
+ const int cbuf0_size =
+ ilo_shader_get_kernel_param(ilo->fs, ILO_KERNEL_PCB_CBUF0_SIZE);
- size += gen7->estimate_state_size(p->dev,
- ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, pcb_size);
+ size += ilo_gpe_gen7_estimate_state_size(p->dev,
+ ILO_GPE_GEN7_PUSH_CONSTANT_BUFFER, cbuf0_size);
}
return size;
enum ilo_3d_pipeline_action action,
const void *arg)
{
- const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
int size;
switch (action) {
{
const struct ilo_context *ilo = arg;
- size = gen7_pipeline_estimate_commands(p, gen7, ilo) +
- gen7_pipeline_estimate_states(p, gen7, ilo);
+ size = gen7_pipeline_estimate_commands(p, ilo) +
+ gen7_pipeline_estimate_states(p, ilo);
}
break;
case ILO_3D_PIPELINE_FLUSH:
case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
- size = gen7->estimate_command_size(p->dev,
+ size = ilo_gpe_gen7_estimate_command_size(p->dev,
ILO_GPE_GEN7_PIPE_CONTROL, 1);
break;
+ case ILO_3D_PIPELINE_WRITE_STATISTICS:
+ {
+ const int num_regs = 10;
+ const int num_pads = 1;
+
+ size = ilo_gpe_gen7_estimate_command_size(p->dev,
+ ILO_GPE_GEN7_PIPE_CONTROL, 1);
+ size += ilo_gpe_gen7_estimate_command_size(p->dev,
+ ILO_GPE_GEN7_MI_STORE_REGISTER_MEM, 1) * 2 * num_regs;
+ size += ilo_gpe_gen7_estimate_command_size(p->dev,
+ ILO_GPE_GEN7_MI_STORE_DATA_IMM, 1) * num_pads;
+ }
+ break;
+ case ILO_3D_PIPELINE_RECTLIST:
+ size = 64 + 256; /* states + commands */
+ break;
default:
assert(!"unknown 3D pipeline action");
size = 0;
void
ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
{
- const struct ilo_gpe_gen7 *gen7 = ilo_gpe_gen7_get();
-
p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
-
-#define GEN6_USE(p, name, from) \
- p->gen6_ ## name = from->emit_ ## name
- GEN6_USE(p, STATE_BASE_ADDRESS, gen7);
- GEN6_USE(p, STATE_SIP, gen7);
- GEN6_USE(p, PIPELINE_SELECT, gen7);
- GEN6_USE(p, 3DSTATE_VERTEX_BUFFERS, gen7);
- GEN6_USE(p, 3DSTATE_VERTEX_ELEMENTS, gen7);
- GEN6_USE(p, 3DSTATE_INDEX_BUFFER, gen7);
- GEN6_USE(p, 3DSTATE_VF_STATISTICS, gen7);
- GEN6_USE(p, 3DSTATE_SCISSOR_STATE_POINTERS, gen7);
- GEN6_USE(p, 3DSTATE_VS, gen7);
- GEN6_USE(p, 3DSTATE_CLIP, gen7);
- GEN6_USE(p, 3DSTATE_CONSTANT_VS, gen7);
- GEN6_USE(p, 3DSTATE_CONSTANT_GS, gen7);
- GEN6_USE(p, 3DSTATE_CONSTANT_PS, gen7);
- GEN6_USE(p, 3DSTATE_DRAWING_RECTANGLE, gen7);
- GEN6_USE(p, 3DSTATE_POLY_STIPPLE_OFFSET, gen7);
- GEN6_USE(p, 3DSTATE_POLY_STIPPLE_PATTERN, gen7);
- GEN6_USE(p, 3DSTATE_LINE_STIPPLE, gen7);
- GEN6_USE(p, 3DSTATE_AA_LINE_PARAMETERS, gen7);
- GEN6_USE(p, 3DSTATE_MULTISAMPLE, gen7);
- GEN6_USE(p, 3DSTATE_STENCIL_BUFFER, gen7);
- GEN6_USE(p, 3DSTATE_HIER_DEPTH_BUFFER, gen7);
- GEN6_USE(p, 3DSTATE_CLEAR_PARAMS, gen7);
- GEN6_USE(p, PIPE_CONTROL, gen7);
- GEN6_USE(p, 3DPRIMITIVE, gen7);
- GEN6_USE(p, INTERFACE_DESCRIPTOR_DATA, gen7);
- GEN6_USE(p, CC_VIEWPORT, gen7);
- GEN6_USE(p, COLOR_CALC_STATE, gen7);
- GEN6_USE(p, BLEND_STATE, gen7);
- GEN6_USE(p, DEPTH_STENCIL_STATE, gen7);
- GEN6_USE(p, SCISSOR_RECT, gen7);
- GEN6_USE(p, BINDING_TABLE_STATE, gen7);
- GEN6_USE(p, surf_SURFACE_STATE, gen7);
- GEN6_USE(p, view_SURFACE_STATE, gen7);
- GEN6_USE(p, cbuf_SURFACE_STATE, gen7);
- GEN6_USE(p, SAMPLER_STATE, gen7);
- GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen7);
- GEN6_USE(p, push_constant_buffer, gen7);
-#undef GEN6_USE
-
-#define GEN7_USE(p, name, from) \
- p->gen7_ ## name = from->emit_ ## name
- GEN7_USE(p, 3DSTATE_DEPTH_BUFFER, gen7);
- GEN7_USE(p, 3DSTATE_CC_STATE_POINTERS, gen7);
- GEN7_USE(p, 3DSTATE_GS, gen7);
- GEN7_USE(p, 3DSTATE_SF, gen7);
- GEN7_USE(p, 3DSTATE_WM, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLE_MASK, gen7);
- GEN7_USE(p, 3DSTATE_CONSTANT_HS, gen7);
- GEN7_USE(p, 3DSTATE_CONSTANT_DS, gen7);
- GEN7_USE(p, 3DSTATE_HS, gen7);
- GEN7_USE(p, 3DSTATE_TE, gen7);
- GEN7_USE(p, 3DSTATE_DS, gen7);
- GEN7_USE(p, 3DSTATE_STREAMOUT, gen7);
- GEN7_USE(p, 3DSTATE_SBE, gen7);
- GEN7_USE(p, 3DSTATE_PS, gen7);
- GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP, gen7);
- GEN7_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS_CC, gen7);
- GEN7_USE(p, 3DSTATE_BLEND_STATE_POINTERS, gen7);
- GEN7_USE(p, 3DSTATE_DEPTH_STENCIL_STATE_POINTERS, gen7);
- GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_VS, gen7);
- GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_HS, gen7);
- GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_DS, gen7);
- GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_GS, gen7);
- GEN7_USE(p, 3DSTATE_BINDING_TABLE_POINTERS_PS, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_VS, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_HS, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_DS, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_GS, gen7);
- GEN7_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS_PS, gen7);
- GEN7_USE(p, 3DSTATE_URB_VS, gen7);
- GEN7_USE(p, 3DSTATE_URB_HS, gen7);
- GEN7_USE(p, 3DSTATE_URB_DS, gen7);
- GEN7_USE(p, 3DSTATE_URB_GS, gen7);
- GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_VS, gen7);
- GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_HS, gen7);
- GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_DS, gen7);
- GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_GS, gen7);
- GEN7_USE(p, 3DSTATE_PUSH_CONSTANT_ALLOC_PS, gen7);
- GEN7_USE(p, 3DSTATE_SO_DECL_LIST, gen7);
- GEN7_USE(p, 3DSTATE_SO_BUFFER, gen7);
- GEN7_USE(p, SF_CLIP_VIEWPORT, gen7);
-#undef GEN7_USE
+ p->emit_write_statistics = ilo_3d_pipeline_emit_write_statistics_gen6;
+ p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen7;
}
projects / mesa.git / blobdiff