#define ILO_WM_CONST_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + i)
#define ILO_WM_TEXTURE_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + ILO_MAX_CONST_BUFFERS + i)
+struct ilo_buffer;
+struct ilo_texture;
+
struct ilo_vb_state {
struct pipe_vertex_buffer states[PIPE_MAX_ATTRIBS];
uint32_t enabled_mask;
struct pipe_index_buffer state;
};
+struct ilo_ve_cso {
+ /* VERTEX_ELEMENT_STATE */
+ uint32_t payload[2];
+};
+
struct ilo_ve_state {
- struct pipe_vertex_element states[PIPE_MAX_ATTRIBS];
+ struct ilo_ve_cso cso[PIPE_MAX_ATTRIBS];
unsigned count;
+
+ unsigned instance_divisors[PIPE_MAX_ATTRIBS];
+ unsigned vb_mapping[PIPE_MAX_ATTRIBS];
+ unsigned vb_count;
};
struct ilo_so_state {
uint32_t payload[ILO_MAX_VIEWPORTS * 2];
};
+struct ilo_rasterizer_clip {
+ /* 3DSTATE_CLIP */
+ uint32_t payload[3];
+
+ uint32_t can_enable_guardband;
+};
+
+struct ilo_rasterizer_sf {
+ /* 3DSTATE_SF */
+ uint32_t payload[6];
+ uint32_t dw_msaa;
+};
+
struct ilo_rasterizer_state {
struct pipe_rasterizer_state state;
+
+ struct ilo_rasterizer_clip clip;
+ struct ilo_rasterizer_sf sf;
};
struct ilo_dsa_state {
- struct pipe_depth_stencil_alpha_state state;
+ /* DEPTH_STENCIL_STATE */
+ uint32_t payload[3];
+
+ struct pipe_alpha_state alpha;
};
struct ilo_blend_cso {
unsigned count;
};
+struct ilo_view_surface {
+ /* SURFACE_STATE */
+ uint32_t payload[8];
+ struct intel_bo *bo;
+};
+
+struct ilo_view_cso {
+ struct pipe_sampler_view base;
+
+ struct ilo_view_surface surface;
+};
+
struct ilo_view_state {
struct pipe_sampler_view *states[ILO_MAX_SAMPLER_VIEWS];
unsigned count;
};
+struct ilo_cbuf_cso {
+ struct pipe_resource *resource;
+ struct ilo_view_surface surface;
+};
+
struct ilo_cbuf_state {
- struct pipe_constant_buffer states[ILO_MAX_CONST_BUFFERS];
+ struct ilo_cbuf_cso cso[ILO_MAX_CONST_BUFFERS];
unsigned count;
};
unsigned count;
};
+struct ilo_surface_cso {
+ struct pipe_surface base;
+
+ bool is_rt;
+ union {
+ struct ilo_view_surface rt;
+ struct ilo_zs_surface {
+ uint32_t payload[10];
+ struct intel_bo *bo;
+ struct intel_bo *hiz_bo;
+ struct intel_bo *separate_s8_bo;
+ } zs;
+ } u;
+};
+
struct ilo_fb_state {
struct pipe_framebuffer_state state;
+ struct ilo_zs_surface null_zs;
unsigned num_samples;
};
unsigned count;
};
+void
+ilo_gpe_init_ve(const struct ilo_dev_info *dev,
+ unsigned num_states,
+ const struct pipe_vertex_element *states,
+ struct ilo_ve_state *ve);
+
void
ilo_gpe_set_viewport_cso(const struct ilo_dev_info *dev,
const struct pipe_viewport_state *state,
ilo_gpe_set_scissor_null(const struct ilo_dev_info *dev,
struct ilo_scissor_state *scissor);
+void
+ilo_gpe_init_rasterizer_clip(const struct ilo_dev_info *dev,
+ const struct pipe_rasterizer_state *state,
+ struct ilo_rasterizer_clip *clip);
+
+void
+ilo_gpe_init_rasterizer_sf(const struct ilo_dev_info *dev,
+ const struct pipe_rasterizer_state *state,
+ struct ilo_rasterizer_sf *sf);
+
+static inline void
+ilo_gpe_init_rasterizer(const struct ilo_dev_info *dev,
+ const struct pipe_rasterizer_state *state,
+ struct ilo_rasterizer_state *rasterizer)
+{
+ ilo_gpe_init_rasterizer_clip(dev, state, &rasterizer->clip);
+ ilo_gpe_init_rasterizer_sf(dev, state, &rasterizer->sf);
+}
+
+void
+ilo_gpe_init_dsa(const struct ilo_dev_info *dev,
+ const struct pipe_depth_stencil_alpha_state *state,
+ struct ilo_dsa_state *dsa);
+
void
ilo_gpe_init_blend(const struct ilo_dev_info *dev,
const struct pipe_blend_state *state,
const struct pipe_sampler_state *state,
struct ilo_sampler_cso *sampler);
+void
+ilo_gpe_init_view_surface_null_gen6(const struct ilo_dev_info *dev,
+ unsigned width, unsigned height,
+ unsigned depth, unsigned level,
+ struct ilo_view_surface *surf);
+
+void
+ilo_gpe_init_view_surface_for_buffer_gen6(const struct ilo_dev_info *dev,
+ const struct ilo_buffer *buf,
+ unsigned offset, unsigned size,
+ unsigned struct_size,
+ enum pipe_format elem_format,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf);
+
+void
+ilo_gpe_init_view_surface_for_texture_gen6(const struct ilo_dev_info *dev,
+ const struct ilo_texture *tex,
+ enum pipe_format format,
+ unsigned first_level,
+ unsigned num_levels,
+ unsigned first_layer,
+ unsigned num_layers,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf);
+
+void
+ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev,
+ unsigned width, unsigned height,
+ unsigned depth, unsigned level,
+ struct ilo_view_surface *surf);
+
+void
+ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev,
+ const struct ilo_buffer *buf,
+ unsigned offset, unsigned size,
+ unsigned struct_size,
+ enum pipe_format elem_format,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf);
+
+void
+ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev,
+ const struct ilo_texture *tex,
+ enum pipe_format format,
+ unsigned first_level,
+ unsigned num_levels,
+ unsigned first_layer,
+ unsigned num_layers,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf);
+
+static inline void
+ilo_gpe_init_view_surface_null(const struct ilo_dev_info *dev,
+ unsigned width, unsigned height,
+ unsigned depth, unsigned level,
+ struct ilo_view_surface *surf)
+{
+ if (dev->gen >= ILO_GEN(7)) {
+ ilo_gpe_init_view_surface_null_gen7(dev,
+ width, height, depth, level, surf);
+ }
+ else {
+ ilo_gpe_init_view_surface_null_gen6(dev,
+ width, height, depth, level, surf);
+ }
+}
+
+static inline void
+ilo_gpe_init_view_surface_for_buffer(const struct ilo_dev_info *dev,
+ const struct ilo_buffer *buf,
+ unsigned offset, unsigned size,
+ unsigned struct_size,
+ enum pipe_format elem_format,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf)
+{
+ if (dev->gen >= ILO_GEN(7)) {
+ ilo_gpe_init_view_surface_for_buffer_gen7(dev, buf, offset, size,
+ struct_size, elem_format, is_rt, render_cache_rw, surf);
+ }
+ else {
+ ilo_gpe_init_view_surface_for_buffer_gen6(dev, buf, offset, size,
+ struct_size, elem_format, is_rt, render_cache_rw, surf);
+ }
+}
+
+static inline void
+ilo_gpe_init_view_surface_for_texture(const struct ilo_dev_info *dev,
+ const struct ilo_texture *tex,
+ enum pipe_format format,
+ unsigned first_level,
+ unsigned num_levels,
+ unsigned first_layer,
+ unsigned num_layers,
+ bool is_rt, bool render_cache_rw,
+ struct ilo_view_surface *surf)
+{
+ if (dev->gen >= ILO_GEN(7)) {
+ ilo_gpe_init_view_surface_for_texture_gen7(dev, tex, format,
+ first_level, num_levels, first_layer, num_layers,
+ is_rt, render_cache_rw, surf);
+ }
+ else {
+ ilo_gpe_init_view_surface_for_texture_gen6(dev, tex, format,
+ first_level, num_levels, first_layer, num_layers,
+ is_rt, render_cache_rw, surf);
+ }
+}
+
+void
+ilo_gpe_init_zs_surface(const struct ilo_dev_info *dev,
+ const struct ilo_texture *tex,
+ enum pipe_format format,
+ unsigned level,
+ unsigned first_layer, unsigned num_layers,
+ struct ilo_zs_surface *zs);
+
#endif /* ILO_GPE_H */